Analysis of soft error rate in flip-flops and scannable latches

Proceedings - IEEE International SOC Conference, SOCC 2003

Volumn , Issue , 2003, Pages 231-234

  Ramanarayanan, R ^a   Degalahal, V ^a   Vijaykrishnan, N ^a   Irwin, M J ^a   Duarte, D ^a,b  

^a PENNSYLVANIA STATE UNIVERSITY   (United States)

^b INTEL CORPORATION   (United States)

Author keywords

Analytical models; Capacitance; Circuit simulation; CMOS technology; Error analysis; Flip flops; Latches; Master slave; Performance analysis; Robustness

Indexed keywords

ANALYTICAL MODELS; CAPACITANCE; CIRCUIT SIMULATION; CMOS INTEGRATED CIRCUITS; ERROR ANALYSIS; ERROR CORRECTION; ERRORS; MICROPROCESSOR CHIPS; RADIATION HARDENING; ROBUSTNESS (CONTROL SYSTEMS);

CMOS TECHNOLOGY; CRITICAL CHARGE; GATE CAPACITANCE; MASTER SLAVE; MASTER-SLAVE FLIP-FLOP; PERFORMANCE ANALYSIS; PIPELINED ARCHITECTURE; RADIATION SOURCE;

FLIP FLOP CIRCUITS;

EID: 70449462530     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/SOC.2003.1241499     Document Type: Conference Paper

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