Off-chip latency-driven dynamic voltage and frequency scaling for an MPEG decoding

Proceedings - Design Automation Conference

Volumn , Issue , 2004, Pages 544-549

  Choi, Kihwan ^a   Soma, Ramakrishna ^a   Pedram, Massoud ^a  

^a UNIVERSITY OF SOUTHERN CALIFORNIA   (United States)

Author keywords

Low power; MPEG decoding; Voltage and frequency scaling

Indexed keywords

CMOS INTEGRATED CIRCUITS; COMPUTATIONAL METHODS; DECODING; ELECTRIC FREQUENCY CONTROL; MICROPROCESSOR CHIPS; PROGRAM PROCESSORS; QUALITY OF SERVICE; VLSI CIRCUITS; VOLTAGE CONTROL;

LOW POWER; MPEG DECODING; PERFORMANCE MONITORING; VOLTAGE AND FREQUENCY SCALING;

TELECOMMUNICATION SYSTEMS;

EID: 4444264518     PISSN: 0738100X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/996566.996718     Document Type: Conference Paper

References (24)

1. M. Horowitz, T. Indermaur, and R. Gonzalez, "Low-power digital design," IEEE Symp. On Low Power Electronics, 1994, pp. 8-11.
2. Developer manual: "Intel 80200 Processor Based on Intel XSoale Microarchitecture,"
3. http://developer.intel.com/design/iio/manuals/273411.htm
4. "Cruso SE Processor TM5800 Data Book v2.1," http://www.transmeta.com/everywhere/products/embedded/embedded_sefa mily.html.
5. F. Yao, A. Demers, and S. Shenker, " A scheduling model for reduced CPU energy," IEEE Annual Foundations of Computer Science, 1995, pp.374-382
6. T. Ishihara and H. Yasuura, "Voltage scheduling problem for dynamically variable voltage processors," Proc. Int'l Symp. on Low Power Electronics and Design, Monterey, CA, Aug. 1998, pp.197-202.
7. D. Shin, J. Kim, and S. Lee, "Low-energy intra-task voltage scheduling using static timing analysis," Proc. Design Automation Conf. 2001, pp. 438-443.
8. I. Hong, G. Qu, M. Potkonjak, and M.B. Srivastava, "Power optimization of variable-voltage core-based systems," IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, Vol.18, No.12, December 1999, pp. 1702-1714
9. G. Quan and X. Hu, "Minimum energy fixed-priority scheduling for variable voltage processors," Proc. Design Automation and Test in Europe, March 2002, pp. 782-787.
10. T. Pering, T. Burd, and R. Broderson, "The simulation and evaluation of dynamic voltage scaling algorithms," Proc. Int 'I Symp. on Low Power Electronics and Design, 1998, pp.76-81.
11. J. Pouwelse, K. Langendoen, R. Lagendijk, and H. Sips, "Power-aware video decoding," 22nd Picture Coding Symp., Seoul, Korea, 2001.
12. D. Son, C. Yu, and H. Kim, "Dynamic voltage scaling on MPEG decoding," Int'l Conf. of Parallel and Distributed System, June 2001
13. D. Grunwald, P. Levis, K. Farkas, C. Money III, and M. Neufeld, "Policies for dynamic clock scheduling," Symp. on Operating Systems Design & Implementation, Oct. 2000
14. K. Choi, K. Dantu, W. Cheng, and M. Pedram, "Frame-based dynamic voltage and frequency scaling for a MPEG decoder," Proc. Int'l Conf. on Computer Aided Design, November 2002, pp. 732-37
15. C. Im, H. Kim, and S. Ha, "Dynamic voltage scheduling technique for low-power multimedia applications using buffers," Proc. Int'l Symp. on Low Power Electronics and Design, Aug. 2001, pp.34-39
16. Z. Lu, J. Lach, M. Stan, K. Skadron, "Reducing multimedia decode power using feedback control," Proc. Int'l Conf. on Computer Design San Jose, CA, Oct. 2003.
17. C. Hsu and U. Kremer, "Compiler-directed dynamic voltage scaling for memory-bound applications," Technical Report DCS-TR-498, Department of Computer Science, Rutgers University, Aug. 2002.
18. C. Hsu and U. Kremer, "Single region vs. multiple regions: A comparison of different compiler-directed dynamic voltage scheduling approaches," Proc. Workshop on Power-Aware Computer Systems, Feb. 2002.
19. D. Marculescu, "On the use of microarchitecture-driven dynamic voltage scaling," Proc. Workshop on Complexity-Effective Design, June 2000.
20. S. Ghiasi, J. Casmira, and D. Grunwald, "Using IPC variation in workloads with externally specified rates to reduce power consumption," Workshop on Complexity Effective Design, June 2000.
21. A. Weissel and F. Bellosa, "Process Cruise Control," Proc. Compilers, Architectures and Synthesis for Embedded Systems, October 2002, pp.238-246
22. http://bmrc.berkeley.edu/frame/research/mpeg.
23. R. Floyd and L. Steinberg, "An adaptive algorithm for spatial grayscale," Proc. the Society for Information Display, 17 (2), 1976, pp. 75-77
24. st Symp. on Operating Systems Design Implementation, 1994, pp. 13-23.