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Volumn , Issue , 2002, Pages 251-254

Dynamic Vt SRAM: A leakage tolerant cache memory for low voltage microprocessors

Author keywords

[No Author keywords available]

Indexed keywords

CACHE MEMORY; COMPUTER SIMULATION; INTEGRATED CIRCUIT LAYOUT; MICROPROCESSOR CHIPS; THRESHOLD VOLTAGE; VLSI CIRCUITS;

EID: 0036949567     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper
Times cited : (68)

References (9)
  • 1
    • 0032592096 scopus 로고    scopus 로고
    • Design challenges of technology scaling
    • July
    • S. Borkar, "Design Challenges of Technology Scaling", IEEE Micro, 19(4):23-29, July 1999.
    • (1999) IEEE Micro , vol.19 , Issue.4 , pp. 23-29
    • Borkar, S.1
  • 2
    • 0033645390 scopus 로고    scopus 로고
    • Gated-Vdd: A circuit technique to reduce leakage in cache memories
    • July
    • M. Powell, S. Yang, B. Falsafi, et al, "Gated-Vdd: A Circuit Technique to Reduce Leakage in Cache Memories", ISLPED, pp.90-95, July 2000.
    • (2000) ISLPED , pp. 90-95
    • Powell, M.1    Yang, S.2    Falsafi, B.3
  • 3
    • 0012530633 scopus 로고    scopus 로고
    • Private communication
    • V. De, Private communication
    • De, V.1
  • 4
    • 0033221245 scopus 로고    scopus 로고
    • An 18-μA standby current 1.8-V, 200-MHz microprocessor with self-substrate-biased data-retention mode
    • nov
    • H. Mizuno, K. Ishibashi, T. Shimura, et al., "An 18-μA Standby Current 1.8-V, 200-MHz Microprocessor with Self-Substrate-Biased Data-Retention Mode", IEEE JSSC, vol. 34, no. 11, nov 1999.
    • (1999) IEEE JSSC , vol.34 , Issue.11
    • Mizuno, H.1    Ishibashi, K.2    Shimura, T.3
  • 6
    • 0036051046 scopus 로고    scopus 로고
    • DRG-cache: A data retention gated-ground cache for low power
    • to be published
    • A. Agarwal, H. Li, and K. Roy, "DRG-Cache: A Data Retention Gated-Ground Cache for Low Power", DAC, to be published, 2002.
    • (2002) DAC
    • Agarwal, A.1    Li, H.2    Roy, K.3
  • 7
    • 0034856732 scopus 로고    scopus 로고
    • Cache decay: Exploiting generational behavior to reduce cache leakage power
    • S. Kaxiras, Z. Hu and M. Martonosi, "Cache Decay: Exploiting Generational Behavior to Reduce Cache Leakage Power", ISCA, pp. 240-251, 2001.
    • (2001) ISCA , pp. 240-251
    • Kaxiras, S.1    Hu, Z.2    Martonosi, M.3
  • 9
    • 0030285492 scopus 로고    scopus 로고
    • 2, 2-D discrete cosine transform core processor with variable threshold-voltage scheme
    • nov
    • 2, 2-D Discrete Cosine Transform Core Processor with Variable Threshold-Voltage Scheme," IEEE JSSC, vol. 31, no. 11, nov 1996.
    • (1996) IEEE JSSC , vol.31 , Issue.11
    • Kuroda, T.1    Fujita, T.2    Mita, S.3


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.