A noise tolerant cache design to reduce gate and sub-threshold leakage in the nanometer regime

Proceedings of the International Symposium on Low Power Electronics and Design

Volumn 2003-January, Issue , 2003, Pages 18-21

  Agarwal, A ^a   Roy, K ^a  

^a Purdue University   (United States)

Author keywords

CMOS technology; Diodes; Gate leakage; Leakage current; MOSFETs; Noise reduction; Power dissipation; Predictive models; Random access memory; Tunneling

Indexed keywords

CACHE MEMORY; CMOS INTEGRATED CIRCUITS; DIODES; ELECTRIC LOSSES; ELECTRON TUNNELING; ENERGY DISSIPATION; INTEGRATED CIRCUIT DESIGN; LEAKAGE CURRENTS; LOW POWER ELECTRONICS; MICROPROCESSOR CHIPS; NOISE ABATEMENT; POWER ELECTRONICS; RANDOM ACCESS STORAGE; STATIC RANDOM ACCESS STORAGE;

CMOS TECHNOLOGY; GATE LEAKAGES; MOSFETS; PREDICTIVE MODELS; RANDOM ACCESS MEMORY;

MOSFET DEVICES;

EID: 1542329510     PISSN: 15334678     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/LPE.2003.1231827     Document Type: Conference Paper

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