Techniques to reduce the soft error rate of a high-performance microprocessor

Conference Proceedings - Annual International Symposium on Computer Architecture, ISCA

Volumn 31, Issue , 2004, Pages 264-275

  Weaver, Christopher ^a   Emer, Joel ^a   Mukherjee, Shubhendu S ^a   Reinhardt, Steven K ^a,b  

^a INTEL CORPORATION   (United States)

^b UNIVERSITY OF MICHIGAN   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

DIFFUSION NODES; FALSE ERRORS; SOFT ERROR RATE; SQUASHING;

BIT ERROR RATE; COMPUTER SOFTWARE; COMPUTER SYSTEM RECOVERY; DATA STORAGE EQUIPMENT; DEMODULATION; FAULT TOLERANT COMPUTER SYSTEMS; SIGNAL PROCESSING; TRANSISTORS;

MICROPROCESSOR CHIPS;

EID: 4644320531     PISSN: 10636897     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (32)

1. H. Ando, et al., "A 13 GHz Fifth Generation SPARC64 Microprocessor," International Solid-State Circuits Conference (ISSCC), 2003.
2. T. Austin, "DIVA: A Reliable Substrate for Deep Submicron Microarchitecture Design," ACM/IEEE 32nd Annual Symposium on Microarchitecture (MICRO-32), November 1999.
3. A. Baniasadi and A. Moshovos, "Instruction Flow-Based Front-end Throttling for Power-Aware High-Performance Processors," International Symposium on Low Power Electronics and Design, 2001.
4. D. Bossen, "CMOS Soft Errors and Server Design," 2002 IRPS Tutorial Notes - Reliability Fundamentals," April 7, 2002.
5. J. Adam Butts and G.S. Sohi, "Dynamic Dead-Instruction Detection and Elimination," 10th International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS), October 2002.
6. T. Calin, et al., "Topology-Related Upset Mechanisms in Design Hardened Storage Cells," Radiation and Its Effects on Components and Systems, 1997. RADECS 97. Fourth European Conference on, 15-19 Sept. 1997.
7. J. Emer, P. Ahuja, N. Binkert, E. Borch, R. Espasa, T. Juan, A. Klauser, C.-K. Luk, S. Manne, S. S. Mukherjee, H. Patil, and S.Wallace, "Asim: A Performance Model Framework," IEEE Computer, 35(2):68-76, Feb. 2002.
8. M. Gomaa, C. Scarbrough, T.N. Vijaykumar, and I. Pomeranz, "Transient Fault Recovery for Chip Multiprocessors," International Symposium on Computer Architecture (ISCA), 2003
9. S. Hareland, J. Maiz, M. Alavi, K. Mistry, S. Walstra, and C. Dai, "Impact of CMOS Scaling and SOI on soft error rates of logic processes," VLSI Technology Digest of Technical Papers, 2001.
10. Intel, "Intel Itanium® Architecture Software Developer's Manual," Intel Corporation, 2002.
11. T. Karnik, B. Bloechel, K. Soumyanath, V. De, and S. Borkar, "Scaling trends of Cosmic Rays induced Soft Errors in static latches beyond 0.18μ," Symposium on VLSI Circuits Digest of Technical Papers, 2001.
12. S. Kim and A.K. Somani, "Soft Error Sensitivity Characterization for Microprocessor Dependability Enhancement Strategy," International Conference on Dependable Systems and Networks (DSN), 2002.
13. K. Krewell, "Intel's McKinley Comes Into View," Microprocessor Report, Volume 15, Archive 10, October 2001.
14. S.-C. Lai, S.-L. Lu, K. Lai and J.-K. Peir, "Ditto Processor," International Conference on Dependable Systems and Networks (DSN), 2002.
15. S. A. Mahlke, W. Y. Chen, W. W. Hwu, B. R. Rau, and M. S. Schlansker, "Sentinel Scheduling for VLIW and Superscalar Pro cessors," 5th International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS), Oct. 1992.
16. S. S. Mukherjee, T. Possum, J. Emer, and S. K. Reinhardt, "Cache Scrubbing in Microprocessors: Myth or Necessity?" 10th International Symposium on Pacific Rim Dependable Computing (PRDC), Papeete, Tahiti, March 2004.
17. S. S. Mukherjee, M. Kontz, and S. K. Reinhardt, "Detailed Design and Evaluation of Redundant Multithreading Alternatives," 29th Annual International Symposium on Computer Architecture (ISCA), 2002.
18. S. S. Mukherjee, C. T. Weaver, J. Emer, S. K. Reinhardt, and T. Austin, "A Systematic Methodology to Compute the Architectural Vulnerability Factors for a High-Performance Microprocessor," 36th Annual International Symposium on Microarchitecture (MICRO), December 2003.
19. J. Ray, J. Hoe, and B. Falsafi, "Dual Use of Superscalar Datapath for Transient-Fault Detection and Recovery," International Symposium on Microarchitecture (MICRO), December 2001.
20. S. K. Reinhardt and S. S. Mukherjee, "Transient Fault Detection via Simultaneous Multithreading," 27th Annual International Symposium on Computer Architecture (ISCA), June 2000.
21. A. Rogers and K. Li, "Software Support for Speculative Loads," 5th International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS), pp. 38-50, Oct. 1992.
22. E. Rotenberg, "AR-SMT: A Microarchitectural Approach to Fault Tolerance in Microprocessors," Proceedings of the Fault-Tolerant Computing Systems (FTCS), 1999.
23. T. Sherwood, E. Perelman, G. Hamerly, and B. Calder, "Automatically Characterizing Large Scale Program Behavior," 10th International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS), October 2002.
24. P. Shivakumar, M. Kistler, S.W. Keckler, D. Burger, and L. Alvisi, "Modeling the Effect of Technology Trends on the Soft Error Rate of Combinatorial Logic," Dependable Systems and Networks (DSN), 2002.
25. D. R. Siewiorek and R. S. Swarz, "Reliable Computer Systems Design and Evaluation," Published by A.K.Peters, Ltd., 1998.
26. T.J. Siegel, et al., "IBM's S/390 G5 Microprocessor Design," IEEE Micro, pp 12-23, Mach/April 1999.
27. J.E. Smith and A.R. Plezkun, "Implementing Precise Interrupts in Pipelined Processors," IEEE Transactions On Computers, 37:5 (May), pp. 562-573, 1988.
28. D. Tullsen and J. A. Brown, "Handling Long-Latency Loads in a Simultaneous Multithreaded Processor," 34th Annual International Symposium on Microarchitecture (MICRO), Dec. 2001.
29. T.N. Vijaykumar, I. Pomeranz, and K. Cheng., "Transient Fault Recovery via Simultaneous Multithreading," International Symposium on Computer Architecture (ISCA), 2002
30. N. Wang, M. Fertig, and S. Patel, "Y-Branches: When You Come to a Fork in the Road, Take It," 12th International Conference on Parallel Architectures and Compilation Techniques (PACT), 2003.
31. N. Wang, J. Quek, T. M. Rafacz, and S. Patel, "Characterizing the Effects of Transient Faults on a High-Performance Processor Pipeline," International Conference on Dependable Systems and Networks, June 2004.
32. J.F. Ziegler, et al., "IBM experiments in soft fails in computer electronics (1978 - 1994)," IBM Journal of Research and Development, pp. 3-18, Volume 40, Number 1, January 1996.