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Volumn 51, Issue 9, 2007, Pages 1185-1193

Specific features of multiple-gate MOSFET threshold voltage and subthreshold slope behavior at high temperatures

Author keywords

FinFETs; High temperature; Multiple gate MOSFETs; Subthreshold slope; Threshold voltage

Indexed keywords

COMPUTER SIMULATION; HIGH TEMPERATURE EFFECTS; MEASUREMENT THEORY; SILICON; THIN FILMS; THRESHOLD VOLTAGE; TRANSISTORS;

EID: 34548539482     PISSN: 00381101     EISSN: None     Source Type: Journal    
DOI: 10.1016/j.sse.2007.07.020     Document Type: Article
Times cited : (28)

References (31)
  • 1
    • 34548531372 scopus 로고    scopus 로고
    • .
  • 3
    • 0041886632 scopus 로고    scopus 로고
    • Ideal rectangular cross-section Si-Fin channel double-gate MOSFETs fabricated using orientation-dependent wet etching
    • Liu Y., Ishii K., Tsutsumi T., Masahara T., and Suzuki E. Ideal rectangular cross-section Si-Fin channel double-gate MOSFETs fabricated using orientation-dependent wet etching. Electron Dev Lett 24 (2003) 484-487
    • (2003) Electron Dev Lett , vol.24 , pp. 484-487
    • Liu, Y.1    Ishii, K.2    Tsutsumi, T.3    Masahara, T.4    Suzuki, E.5
  • 4
    • 0036779146 scopus 로고    scopus 로고
    • Spacer FinFET: nanoscale double-gate CMOS technology for the Terabit era
    • Choi Y.K., King T.J., and Hu C. Spacer FinFET: nanoscale double-gate CMOS technology for the Terabit era. Solid-State Electron 46 (2002) 1595-1601
    • (2002) Solid-State Electron , vol.46 , pp. 1595-1601
    • Choi, Y.K.1    King, T.J.2    Hu, C.3
  • 5
    • 23344432413 scopus 로고    scopus 로고
    • Experimental evaluation of gate architecture influence on DG SOI MOSFETs performance
    • Widiez J., Lolivier J., and Vinet M. Experimental evaluation of gate architecture influence on DG SOI MOSFETs performance. IEEE Trans Electron Dev 52 (2005) 1772-1779
    • (2005) IEEE Trans Electron Dev , vol.52 , pp. 1772-1779
    • Widiez, J.1    Lolivier, J.2    Vinet, M.3
  • 6
    • 0042164579 scopus 로고    scopus 로고
    • Implementation and characterization of the double-gate MOSFET using lateral solid-phase epitaxy
    • Liu H., Xiong Z., and Sin J. Implementation and characterization of the double-gate MOSFET using lateral solid-phase epitaxy. IEEE Trans Electron Dev 50 (2003) 1552-1555
    • (2003) IEEE Trans Electron Dev , vol.50 , pp. 1552-1555
    • Liu, H.1    Xiong, Z.2    Sin, J.3
  • 7
    • 21044452456 scopus 로고    scopus 로고
    • Bonded planar double-metal-gate NMOS transistors down to 10 nm
    • Vinet M., Poiroux T., and Widiez J. Bonded planar double-metal-gate NMOS transistors down to 10 nm. Electron Dev Lett 26 (2005) 317-319
    • (2005) Electron Dev Lett , vol.26 , pp. 317-319
    • Vinet, M.1    Poiroux, T.2    Widiez, J.3
  • 8
    • 16244379510 scopus 로고    scopus 로고
    • Novel process for fully self-aligned planar ultrathin body double-gate FET
    • Shenoy R., and Saraswat K. Novel process for fully self-aligned planar ultrathin body double-gate FET. Proc IEEE Int SOI Conf (2004) 190-191
    • (2004) Proc IEEE Int SOI Conf , pp. 190-191
    • Shenoy, R.1    Saraswat, K.2
  • 9
    • 27144512245 scopus 로고    scopus 로고
    • Henson K, Collaert N, Demand M et al. NMOS and PMOS triple gate devices with mid-gap metal gate on oxynitride and Hf based gate dielectrics. VLSI-TSA-TECH 2005:136-7.
  • 11
    • 0036999661 scopus 로고    scopus 로고
    • Multi-gate SOI MOSFETs: device design guidelines
    • Park J.T., and Colinge J.P. Multi-gate SOI MOSFETs: device design guidelines. IEEE Trans Electron Dev 49 (2002) 2222-2229
    • (2002) IEEE Trans Electron Dev , vol.49 , pp. 2222-2229
    • Park, J.T.1    Colinge, J.P.2
  • 12
    • 29044440093 scopus 로고    scopus 로고
    • FinFET - a self-aligned double-gate MOSFET scalable to 20 nm
    • Hisamoto D., Lee W.-C., Kedzierski J., et al. FinFET - a self-aligned double-gate MOSFET scalable to 20 nm. IEEE Trans Electron Dev 47 (2000) 2320-2325
    • (2000) IEEE Trans Electron Dev , vol.47 , pp. 2320-2325
    • Hisamoto, D.1    Lee, W.-C.2    Kedzierski, J.3
  • 14
    • 0043071349 scopus 로고    scopus 로고
    • 30 nm Self-aligned FinFET with large source/drain fan-out structure
    • Woo D.S., Choi B.Y., Choi V.Y., Lee M.W., Lee J.D., and Park B.G. 30 nm Self-aligned FinFET with large source/drain fan-out structure. Electron Lett 39 (2003) 1154-1155
    • (2003) Electron Lett , vol.39 , pp. 1154-1155
    • Woo, D.S.1    Choi, B.Y.2    Choi, V.Y.3    Lee, M.W.4    Lee, J.D.5    Park, B.G.6
  • 15
    • 3142730186 scopus 로고    scopus 로고
    • Nanoscale FiNFETs for low power applications
    • Rosner W., Landgaf E., Kretz J., et al. Nanoscale FiNFETs for low power applications. Solid-State Electron 48 (2005) 1819-1823
    • (2005) Solid-State Electron , vol.48 , pp. 1819-1823
    • Rosner, W.1    Landgaf, E.2    Kretz, J.3
  • 17
    • 34548535501 scopus 로고    scopus 로고
    • FinFET: the prospective Multiple-gate device for future SoC applications
    • Inaba S., Okano K., and Izumida T. FinFET: the prospective Multiple-gate device for future SoC applications. Proc ESSDERC (2006) 49-53
    • (2006) Proc ESSDERC , pp. 49-53
    • Inaba, S.1    Okano, K.2    Izumida, T.3
  • 18
    • 34548542251 scopus 로고    scopus 로고
    • Analog and RF circuits in 45 nm CMOS and below: planar bulk versus FinFET
    • Wambacq P., Verbruggen B., Scheir K., et al. Analog and RF circuits in 45 nm CMOS and below: planar bulk versus FinFET. Proc ESSDERC (2006) 53-57
    • (2006) Proc ESSDERC , pp. 53-57
    • Wambacq, P.1    Verbruggen, B.2    Scheir, K.3
  • 19
    • 33646023723 scopus 로고    scopus 로고
    • Analog/RF performance of Multiple gate SOI devices: wideband simulations and characterization
    • Raskin J.-P., Chung T.M., Kilchytska V., Lederer D., and Flandre D. Analog/RF performance of Multiple gate SOI devices: wideband simulations and characterization. IEEE Trans Electron Dev 53 (2006) 1088-1096
    • (2006) IEEE Trans Electron Dev , vol.53 , pp. 1088-1096
    • Raskin, J.-P.1    Chung, T.M.2    Kilchytska, V.3    Lederer, D.4    Flandre, D.5
  • 21
    • 84907697695 scopus 로고    scopus 로고
    • Subthreshold characteristics of p-type triple-gate MOSFETs
    • Lemme M., Mollenhauer T., and Henschel W. Subthreshold characteristics of p-type triple-gate MOSFETs. Proc ESSDERC (2003) 123-127
    • (2003) Proc ESSDERC , pp. 123-127
    • Lemme, M.1    Mollenhauer, T.2    Henschel, W.3
  • 24
    • 0042888776 scopus 로고    scopus 로고
    • Threshold voltage and subthreshold slope of Multiple-gate SOI MOSFETs
    • Colinge J.P., Park J.W., and Xiong W. Threshold voltage and subthreshold slope of Multiple-gate SOI MOSFETs. IEEE Electron Dev Lett 24 (2003) 515-517
    • (2003) IEEE Electron Dev Lett , vol.24 , pp. 515-517
    • Colinge, J.P.1    Park, J.W.2    Xiong, W.3
  • 25
    • 34548540324 scopus 로고    scopus 로고
    • Atlas Manual 2005.
  • 27
    • 0029209413 scopus 로고
    • Moderate inversion model of ultrathin double-gate nMOS/SOI transistors
    • Francis P., Terao A., Flandre D., and Van de Wiele F. Moderate inversion model of ultrathin double-gate nMOS/SOI transistors. Solid-State Electron 38 (1995) 171-176
    • (1995) Solid-State Electron , vol.38 , pp. 171-176
    • Francis, P.1    Terao, A.2    Flandre, D.3    Van de Wiele, F.4
  • 28
    • 12344336837 scopus 로고    scopus 로고
    • A design oriented charge-based current model for symmetric DG MOSFET and its correlation with the EKV formalism
    • Sallese J.M., Krummenacher F., Pregaldiny F., Lallement C., Roy A., and Enz C. A design oriented charge-based current model for symmetric DG MOSFET and its correlation with the EKV formalism. Solid-State Electron 49 (2005) 485-489
    • (2005) Solid-State Electron , vol.49 , pp. 485-489
    • Sallese, J.M.1    Krummenacher, F.2    Pregaldiny, F.3    Lallement, C.4    Roy, A.5    Enz, C.6
  • 29
    • 0035694506 scopus 로고    scopus 로고
    • Analytic solutions of charge and capacitance in symmetric and asymmetric double-gate MOSFETs
    • Taur Y. Analytic solutions of charge and capacitance in symmetric and asymmetric double-gate MOSFETs. IEEE Trans Electron Dev 48 (2001) 2861-2869
    • (2001) IEEE Trans Electron Dev , vol.48 , pp. 2861-2869
    • Taur, Y.1
  • 31
    • 0033732282 scopus 로고    scopus 로고
    • An analytic solution to a double-gate MOSFET with undoped body
    • Taur Y. An analytic solution to a double-gate MOSFET with undoped body. IEEE Electron Dev Lett 21 (2000) 245-247
    • (2000) IEEE Electron Dev Lett , vol.21 , pp. 245-247
    • Taur, Y.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.