Novel process for fully self-aligned planar ultrathin body double gate FET

Proceedings - IEEE International SOI Conference

Volumn , Issue , 2004, Pages 190-191

  Shenoy, R S ^a   Saraswat, K C ^a  

^a Stanford University   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

DOUBLE-GATE FET (DGFET); GATE DIELECTRIC; GATE ELECTRODES; SELF-ALIGNED PLANAR ULTRATHIN BODY;

ANISOTROPY; CAPACITANCE; CHEMICAL VAPOR DEPOSITION; CMOS INTEGRATED CIRCUITS; DIELECTRIC MATERIALS; ELECTRODES; ELECTRON MOBILITY; EPITAXIAL GROWTH; SCANNING ELECTRON MICROSCOPY; SINGLE CRYSTALS; THERMOOXIDATION; TRANSMISSION ELECTRON MICROSCOPY;

FIELD EFFECT TRANSISTORS;

EID: 16244379510     PISSN: 1078621X     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (7)

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6. J.-H. Lee et al., IEDM 1999.
7. R. Shenoy et al., IEEE Trans. Nanotechnology. 2, p. 265 (2003).