Bonded planar double-metal-gate NMOS transistors down to 10 nm

IEEE Electron Device Letters

Volumn 26, Issue 5, 2005, Pages 317-319

  Vinet, M ^a   Poiroux, T ^a   Widiez, J ^b   Lolivier, J ^a   Previtali, B ^a   Vizioz, C ^a   Guillaumot, B ^b   Le Tiec, Y ^a   Besson, P ^b   Biasse, B ^a   Allain, F ^a   Casse M ^a   Lafond, D ^a   Hartmann, J M ^a   Morand, Y ^b   Chiaroni, J ^a   Deleonibus, S ^a  

^a CEA LETI   (France)

^b STMICROELECTRONICS   (France)

Author keywords

Double gate; Electrical characterization; Metalgate; MOS transistors; Nano MOSFETs silicon on insulator (SOI); Wafer bonding

Indexed keywords

BONDING; ELECTRIC PROPERTIES; ETCHING; GATES (TRANSISTOR); NANOTECHNOLOGY; SEMICONDUCTOR DEVICE MANUFACTURE; SILICON ON INSULATOR TECHNOLOGY; SILICON WAFERS;

DOUBLE METAL GATE TRANSISTORS; ELECTRICAL CHARACTERIZATION; NANO-MOSFETS; WAFER BONDING;

MOSFET DEVICES;

EID: 21044452456     PISSN: 07413106     EISSN: None     Source Type: Journal    
DOI: 10.1109/LED.2005.846580     Document Type: Article

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