Threshold voltage and subthreshold slope of multiple-gate SOI MOSFETs

IEEE Electron Device Letters

Volumn 24, Issue 8, 2003, Pages 515-517

  Colinge, J P ^a   Park, J W ^b   Xiong, W ^b  

^a University of California   (United States)

^b Kumoh National Institute of Technology   (South Korea)

Author keywords

Insulated gate FETs; MOS devices; Semiconductor device modeling; SOI technology

Indexed keywords

CALCULATIONS; COMPUTER SIMULATION; ELECTRIC CURRENTS; GATES (TRANSISTOR); PERMITTIVITY; SEMICONDUCTOR DEVICE MODELS; SEMICONDUCTOR DEVICE STRUCTURES; SEMICONDUCTOR DOPING; SILICON ON INSULATOR TECHNOLOGY; THRESHOLD VOLTAGE;

CORNER INVERSION EFFECT; CURRENT CONDUCTION; MULTIPLE GATE DEVICE; SUBTHRESHOLD SWING;

MOSFET DEVICES;

EID: 0042888776     PISSN: 07413106     EISSN: None     Source Type: Journal    
DOI: 10.1109/LED.2003.815153     Document Type: Article

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