메뉴 건너뛰기




Volumn 48, Issue 10-11 SPEC. ISS., 2004, Pages 1819-1823

Nanoscale FinFETs for low power applications

Author keywords

Double gate; FinFET; Low power; MOSFET

Indexed keywords

CMOS INTEGRATED CIRCUITS; ELECTRON BEAM LITHOGRAPHY; HOLE MOBILITY; LEAKAGE CURRENTS; PLASMA ETCHING; SEMICONDUCTOR DOPING; SILICON WAFERS;

EID: 3142730186     PISSN: 00381101     EISSN: None     Source Type: Journal    
DOI: 10.1016/j.sse.2004.05.019     Document Type: Conference Paper
Times cited : (21)

References (10)
  • 1
    • 0036923438 scopus 로고    scopus 로고
    • FinFET scaling to 10 nm gate length
    • Yu B., et al. FinFET scaling to 10 nm gate length. Tech. Dig. IEDM. 2002;251-253.
    • (2002) Tech. Dig. IEDM , pp. 251-253
    • Yu, B.1
  • 2
    • 0035717948 scopus 로고    scopus 로고
    • Sub 20 nm CMOS FinFET technologies
    • Choi Y.K., et al. Sub 20 nm CMOS FinFET technologies. Tech. Dig. IEDM. 2001;421-424.
    • (2001) Tech. Dig. IEDM , pp. 421-424
    • Choi, Y.K.1
  • 3
    • 0038104277 scopus 로고    scopus 로고
    • High performance fully-depleted tri-gate CMOS transistors
    • Doyle B.S., et al. High performance fully-depleted tri-gate CMOS transistors. IEEE Electron Dev. Lett. 24:2003;261-263.
    • (2003) IEEE Electron Dev. Lett. , vol.24 , pp. 261-263
    • Doyle, B.S.1
  • 4
    • 0035714369 scopus 로고    scopus 로고
    • High-performance symmetric-gate and CMOS-compatible Vt asymmetric-gate FinFET devices
    • Kedzierski J., et al. High-performance symmetric-gate and CMOS-compatible Vt asymmetric-gate FinFET devices. Tech. Dig. IEDM. 2001;437-440.
    • (2001) Tech. Dig. IEDM , pp. 437-440
    • Kedzierski, J.1
  • 5
    • 0032255808 scopus 로고    scopus 로고
    • A folded-channel MOSFET for deep-sub-tenth micron era
    • Hisamoto D., et al. A folded-channel MOSFET for deep-sub-tenth micron era. Tech. Dig. IEDM. 1998;1032-1034.
    • (1998) Tech. Dig. IEDM , pp. 1032-1034
    • Hisamoto, D.1
  • 6
    • 3142658991 scopus 로고    scopus 로고
    • 20 nm electron beam lithography and reactive ion etching for the fabrication of double gate FinFET devices
    • Kretz J., et al. 20 nm electron beam lithography and reactive ion etching for the fabrication of double gate FinFET devices. Microel. Eng. 763:2003;67-68.
    • (2003) Microel. Eng. , vol.763 , pp. 67-68
    • Kretz, J.1
  • 7
    • 0842266648 scopus 로고    scopus 로고
    • Threshold voltage control in NiSi gated MOSFETs through silicidation induced impurity segregation (SIIS
    • Kedzierski J., et al. Threshold voltage control in NiSi gated MOSFETs through silicidation induced impurity segregation (SIIS. Tech. Dig. IEDM. 2003;315-318.
    • (2003) Tech. Dig. IEDM , pp. 315-318
    • Kedzierski, J.1
  • 8
    • 0036923246 scopus 로고    scopus 로고
    • A 90-nm CMOS device technology with high-speed. General-purpose, and low-leakage transistors for system on chip applications
    • Wu C., et al. A 90-nm CMOS device technology with high-speed. General-purpose, and low-leakage transistors for system on chip applications. Tech. Dig. IEDM. 2002;65-68.
    • (2002) Tech. Dig. IEDM , pp. 65-68
    • Wu, C.1
  • 9
    • 0036045178 scopus 로고    scopus 로고
    • A 100-nm copper/low- K bulk CMOS technology with multi Vt and multi gate oxide integrated transistors for low standby power. High performance and RF/Analog system on chip applications
    • Yeap G.C.-F., et al. A 100-nm copper/low-. K bulk CMOS technology with multi Vt and multi gate oxide integrated transistors for low standby power. High performance and RF/Analog system on chip applications Symp. VLSI Techn. 2002;16-17.
    • (2002) Symp. VLSI Techn. , pp. 16-17
    • Yeap, G.C.-F.1
  • 10
    • 0036051675 scopus 로고    scopus 로고
    • 2 high density embedded SRAM technologies for l00 nm generation SOC and beyond
    • 2 high density embedded SRAM technologies for l00 nm generation SOC and beyond. Symp. VLSI Techn. 2002;14-15.
    • (2002) Symp. VLSI Techn. , pp. 14-15
    • Tomita, K.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.