On the high-temperature subthreshold slope of thin-film SOI MOSFETs

IEEE Electron Device Letters

Volumn 23, Issue 3, 2002, Pages 148-150

  Rudenko, T ^b   Kilchytska, V ^b   Colinge, Jean Pierre ^a,c   Dessard, V ^d   Flandre, Denis ^a,d  

^a IEEE

^b INSTITUTE OF SEMICONDUCTOR PHYSICS   (Ukraine)

^c Davis   (United States)

^d UNIVERSITÉ CATHOLIQUE DE LOUVAIN   (Belgium)

Author keywords

High temperature techniques; MOSFETs; Silicon on insulator (SOI) technology; Thermal factors

Indexed keywords

CAPACITANCE; COMPUTER SIMULATION; ELECTRIC FIELD EFFECTS; HIGH TEMPERATURE EFFECTS; SILICON ON INSULATOR TECHNOLOGY; THIN FILMS;

THERMAL FACTORS;

MOSFET DEVICES;

EID: 0036503676     PISSN: 07413106     EISSN: None     Source Type: Journal    
DOI: 10.1109/55.988820     Document Type: Article

References (6)

1. Demonstration of the potential of accumulation-mode MOS transistors on SOI substrates for high-temperature operation (150-300 ° C)
2. Silicon-on-insulator technology for high temperature metal oxide semiconductor devices and circuits
3. Subthreshold slope in thin-film SOI MOSFETs
4. Ultra-thin SOI MOSFETs at high temperatures
5. Submicron SOI MOSFETs for high temperature operation (300-600 K)