Multi-Gate mosfet design

ESSDERC 2006 - Proceedings of the 36th European Solid-State Device Research Conference

Volumn 2006-January, Issue , 2006, Pages 65-68

  Knoblinger, G ^a   Pacha, C ^b   Kuttner, F ^a   Marshall, A ^c   Russ, C ^b   Haibach, P ^b   Patruno, P ^d   Schulz, T ^b   Arnim, K V ^b   Engelstaedter, J P ^a   Bertolissi, L ^a   Xiong, W ^c,e   Cleavelin, C R ^c   Schruefer, K ^b  

^a INFINEON TECHNOLOGIES AUSTRIA AG   (Austria)

^b INFINEON TECHNOLOGIES AG   (Germany)

^c TEXAS INSTRUMENTS   (United States)

^d PARC TECHNOLOGIQUE DES FONTAINES   (France)

^e Advanced Technology Development Facility (ATDF) Inc   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

DIGITAL DEVICES; FIELD EFFECT TRANSISTORS; INTEGRATED CIRCUIT MANUFACTURE; LOGIC DESIGN; RECONFIGURABLE HARDWARE; SOLID STATE DEVICES;

BUILDING BLOCKES; CIRCUIT DESIGNS; MID-GAP GATE; MULTI-GATE FIELD EFFECT TRANSISTORS; NEW DEVICES; OUTPUT CONDUCTANCE; SELF-HEATING; SPECIFIC EFFECTS;

MOSFET DEVICES;

EID: 84957887297     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ESSDER.2006.307639     Document Type: Conference Paper

References (8)

1. S. Tang et al., "FinFET-A Quasi Planar Double Gate Transistor, " ISSCC Dig. Techn. Papers, pp. 118-119, Feb.2001.
2. B. Doyle et al., "Tri-Gate Fully-Depleted CMOS Transistors: Fabrication, Design and Layout, "VLSI Techn., pp.133-134, 2003.
3. C. Pacha et al., "Circuit Design Issues in Multi-Gate FET CMOS Technologies, " ISSCC Dig. Techn. Papers, pp.420-421, Feb.2006.
4. G. Knoblinger, "Multi-gate MOSFET Design, " Tutorial in the Advanced Solid State Circuits Forum, ISSCC Feb.2006.
5. V. Subramanian et al., "Device and Circuit-Level Analog Performance Trade-Offs: A Comperative Study of Planar Bulk FETs versus FinFETs, " IEDM Dig. Techn. Papers, Dec.2005.
6. C. Leroux et al., "Characterization and Modeling of Hysteresis Phenomena in High k Dielectrics", IEDM pp.737-740, Dec.2004.
7. G. Knoblinger et al., "Design and Evaluation of Basic Analog Circuits in an Emerging MuGFET Technology, " IEEE SOI Conference pp.39- 40, Oct. 2005.
8. C. Russ et. al., "ESD Evaluation of the Emerging MuGFET Technology, " EOS/ESD Symp., pp. 280-289, Sept. 2005.