Analog and RF circuits in 45 nm CMOS and below: Planar bulk versus FinFET

ESSDERC 2006 - Proceedings of the 36th European Solid-State Device Research Conference

Volumn , Issue , 2006, Pages 53-56

  Wambacq, Piet ^b   Verbruggen, Bob ^b   Scheie, Karen ^b   Borremans, Jonathan ^b   De Heyn, Vincent ^a   Van Der Plas, Geert ^a   Mercha, Abdelkarim ^a   Parvais, Bertrand ^a   Subramanian, Vaidy ^c   Jurczak, Malgorzata ^a   Decoutere, Stefaan ^a   Donnay, Stéphane ^a  

^a IMEC   (Belgium)

^b VRIJE UNIVERSITEIT BRUSSEL   (Belgium)

^c UNIVERSITY OF LEUVEN   (Belgium)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER SIMULATION; SCALABILITY; SPEED INDICATORS; TRANSISTORS;

DOWNSCALING; GATE STACKS; PLANAR BULK;

CMOS INTEGRATED CIRCUITS;

EID: 34548542251     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ESSDER.2006.307636     Document Type: Conference Paper

References (10)

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3. B. Parvais et al., "Suitability of FinFET technology for low-power mixed-signal applications", accepted for ICICDT, May 2006.
4. J. Ryckaert et al., "A 16mA UWB 3-5GHz 20Mpulses/s Quadrature Analog Correlation Receiver in 0.18μm CMOS", Proc. ISSCC, pp. 113-114, February 2006.
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8. http://www.itrs.net/Common/2005ITRS/Wireless2005.pdf
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10. F. Ellinger et al., "60 GHz VCO with wideband tuning range fabricated on VLSI SOI CMOS technology", Microwave Symposium Digest, pp. 1329-1333, June 2004.