An application-specific design methodology for on-chip crossbar generation

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 26, Issue 7, 2007, Pages 1283-1296

  Murali, Srinivasan ^a,b   Benini, Luca ^a,c,d   De Micheli, Giovanni ^a,d  

^a IEEE   (United States)

^b STANFORD UNIVERSITY   (United States)

^c UNIVERSITY OF BOLOGNA   (Italy)

^d EPFL   (Switzerland)

Author keywords

Application specific; Bus; Crossbar; Floorplan; Networks on Chips (NoCs); SystemC; Systems on Chips (SoCs); Timing closure

Indexed keywords

COMMUNICATION ARCHITECTURE; NETWORKS ON CHIPS (NOC); SYSTEMS ON CHIPS (SOC);

BUSBARS; COMPUTER AIDED DESIGN; ELECTRIC POWER UTILIZATION; ELECTRIC UTILITIES; ELECTRIC WIRING; LOGIC DESIGN;

MICROPROCESSOR CHIPS;

EID: 34250768259     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCAD.2006.888284     Document Type: Article

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