Design of high-performance system-on-chips using communication architecture tuners

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 23, Issue 5, 2004, Pages 620-636

  Lahiri, Kanishka ^a   Raghunathan, Anand ^a   Lakshminarayana, Ganesh ^b   Dey, Sujit ^c  

^a NEC LABORATORIES AMERICA   (United States)

^b Alphion Corporation   (United States)

^c UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

Bus architectures; Network on chip; On chip communication; Protocols; System on chip (SoC)

Indexed keywords

ALGORITHMS; COMMUNICATION SYSTEMS; MAPPING; OPTIMIZATION; TOPOLOGY;

BUS ARCHITECTURES; NETWORK-ON-CHIP; ON-CHIP COMMUNICATION; SYSTEM-ON-CHIP (SOC);

MICROPROCESSOR CHIPS;

EID: 2542430318     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCAD.2004.826585     Document Type: Article

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