Automated bus generation for multiprocessor SoC design

Proceedings -Design, Automation and Test in Europe, DATE

Volumn , Issue , 2003, Pages 282-287

  Ryu, Kyeong Keol ^a   Mooney, Vincent J ^a  

^a GEORGIA INSTITUTE OF TECHNOLOGY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BUS ARCHITECTURE; GENERAL GLOBAL BUS ARCHITECTURES; IMPACTING FACTOR; MULTI PROCESSOR SYSTEMS; MULTI-PROCESSOR SOC; SOFTWARE PROGRAMMING; SYSTEM-ON-A-CHIP; WIRELESS TRANSMITTER;

APPLICATION SPECIFIC INTEGRATED CIRCUITS; AUTOMATION; COMPUTER ARCHITECTURE; DESIGN; EXHIBITIONS; MICROPROCESSOR CHIPS; ORTHOGONAL FREQUENCY DIVISION MULTIPLEXING;

BUSES;

EID: 14644388576     PISSN: 15301591     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DATE.2003.1253621     Document Type: Conference Paper

References (15)

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