Trapping mechanisms in negative bias temperature stressed p-MOSFETs

Microelectronics Reliability

Volumn 39, Issue 6-7, 1999, Pages 821-826

  Schlünder, Christian ^a,b   Brederlow, Ralf ^a   Wieczorek, Peter ^a   Dahl, Claus ^a   Holz, Jürgen ^a   Röhner, Michael ^a   Kessel, Sylvia ^a   Herold, Volker ^a   Goser, Karl ^b   Weber, Werner ^a   Thewes, Roland ^a  

^a INFINEON TECHNOLOGIES AG   (Germany)

^b TU DORTMUND UNIVERSITY   (Germany)

Author keywords

[No Author keywords available]

Indexed keywords

ANNEALING; DEGRADATION; HOLE TRAPS; HOT CARRIERS; INTERFACES (MATERIALS); THERMAL STRESS;

CHARGE TRAPPING MECHANISM; NEGATIVE BIAS TEMPERATURE STRESS;

MOSFET DEVICES;

EID: 0041358059     PISSN: 00262714     EISSN: None     Source Type: Journal    
DOI: 10.1016/S0026-2714(99)00107-9     Document Type: Article

References (7)

1. K. O. Jeppson and C. M. Svensson, "Negative bias stress of MOS devices at high electric fields and degradation of MNOS devices", J. Appl. Phys, 1977, p. 2004
2. 2 interface", Phys. Rev. B, 1995, p. 4218
3. S. Ogawa, M. Shimaya, and N. Shiono, "Impact of negativebias temperature instability on the lifetime of single-gate CMOS structures with ultrathin (4-6 nm) gate oxides", Jpn. J. Appl. Phys., 1996, p. 1484
4. P. Heremans, R. Bellens, G. Groeseneken, A. v. Schwerin, H. E. Maes, M. Brox, W. Weber, "The mechanisms of hot carrier degradation", in "Hot-carrier design constrains in MOS devices and circuits', C. T. Wang ed., Van Nostrand Reinhold, New York, 1991
5. R. Thewes and W. Weber, "Effects of hot-carrier degradation in analog CMOS circuits", Proc. Conf. "Insulating Films on Semiconductors" (INFOS), and Microelectronic Engineering 36, pp. 285-292, 1997
6. M. Brox, A. v. Schwerin, Q. Wang, and W. Weber, "A model for the time- and bias-dependence of p-MOSFET degradation", IEEE Trans. Electron Devices, 1994, p. 1184
7. R. Thewes, M. Brox, K. F. Goser, and W. Weber, "Hot-carrier degradation of p-MOSFETs under analog operation", IEEE Trans. Electron Devices, 1997, p. 607