Design and optimization of thin film fully depleted vertical surrounding gate (VSG) MOSFETs for enhanced short channel immunity

Solid-State Electronics

Volumn 46, Issue 9, 2002, Pages 1333-1338

  Kranti, Abhinav ^a   Rashmi, R ^a   Haldar, S ^b   Gupta, R S ^a  

^a UNIVERSITY OF DELHI   (India)

^b UNIVERSITY OF DELHI   (India)

Author keywords

Semiconductor device modeling; Short channel effects; Silicon; Vertical surrounding gate MOSFET

Indexed keywords

GATES (TRANSISTOR); OPTIMIZATION; SEMICONDUCTING SILICON; SEMICONDUCTOR DEVICE MODELS; THIN FILMS; THRESHOLD VOLTAGE; ULSI CIRCUITS;

SHORT CHANNEL IMMUNITY; VERTICAL SURROUNDING GATES (VSG);

MOSFET DEVICES;

EID: 0036721817     PISSN: 00381101     EISSN: None     Source Type: Journal    
DOI: 10.1016/S0038-1101(02)00064-3     Document Type: Article

References (12)

1. Scaling the Si MOSFET: From bulk to SOI to bulk
2. Impact of surrounding gate transistor (SGT) for ultra high density LSI's
3. Multi pillar surrounding gate transistor (M-SGT) for compact and high speed circuits
4. Numerical analysis of a cylindrical thin pillar transistor (CYNTHIA)
5. Scaling theory for cylindrical fully-depleted, surrounding gate MOSFET's
6. An analytical 2-dimensional model for optically controlled thin film fully depleted surrounding/cylindrical gate (SGT/CGT) MOSFET
7. A two-dimensional analytical model for thin film fully depleted surrounded gate (SGT) MOSFET
8. An analytical steady-state current-voltage characteristics of short channel fully depleted surrounding gate transistor (FD-SGT)
9. An analytical surrounding gate MOSFET model
10. An analytical model for threshold voltage and I-V characteristics of fully depleted short channel cylindrical/surrounding gate MOSFET
11. An analytical model for optically controlled fully depleted cylindrical/surrounding gate (CGT/SGT) MOSFET