Fringe-induced barrier lowering (FIBL) included threshold voltage model for double-gate MOSFETs

Solid-State Electronics

Volumn 49, Issue 2, 2005, Pages 271-274

  Chen, Qiang ^a,b   Wang, Lihui ^a   Meindl, James D ^a  

^a GEORGIA INSTITUTE OF TECHNOLOGY   (United States)

^b MS 79 ^*  (United States)

Author keywords

Double gate MOSFET; Fringe induced barrier lowering (FIBL); High k; Scaling limit; Threshold voltage

Indexed keywords

DOUBLE-GATE MOSFET; FRINGE-INDUCED BARRIER LOWERING (FIBL); HIGH-K; SCALING LIMIT;

CARRIER CONCENTRATION; COMPUTER SIMULATION; CURRENT DENSITY; DIELECTRIC PROPERTIES; ELECTRIC FIELD EFFECTS; GATES (TRANSISTOR); PERMITTIVITY; THRESHOLD VOLTAGE;

MOSFET DEVICES;

EID: 9544252188     PISSN: 00381101     EISSN: None     Source Type: Journal    
DOI: 10.1016/j.sse.2004.08.008     Document Type: Article

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