Evaluation of performance degradation factors for high-k gate dielectrics in N-channel MOSFETs

Solid-State Electronics

Volumn 48, Issue 2, 2004, Pages 345-349

  Ohata, Akiko ^a  

^a GUNMA UNIVERSITY   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER SIMULATION; DIELECTRIC MATERIALS; ELECTRIC FIELD EFFECTS; SEMICONDUCTOR DOPING;

GATE DIELECTRICS;

MOSFET DEVICES;

EID: 0242335134     PISSN: 00381101     EISSN: None     Source Type: Journal    
DOI: 10.1016/S0038-1101(03)00294-6     Document Type: Article

References (4)

1. Yeap G.C.F., Krishnan S. Fringing-induced barrier lowering (FIBL) in sub-100 nm MOSFETs with high-. k gate dielectrics Electron. Lett. 34(11):1998;1150-1152.
2. Kencke DL, Chen W, Wang H, Mudanai S, Ouyang Q, Tasch A, Banerjee SK. Source-side barrier effects with very high- K dielectrics in 50 nm Si MOSFETs. 57th Annual Device Research Conference Digest, 1999, p. 22-23.
3. Frank D.J., Taur Y., Wong H.P. Generalized scale length for two-dimensional effects in MOSFET's. IEEE Electron Dev. Lett. 19(10):1998;385-387.
4. Cheng B., Cao M., Rao R., Inani A., Voorde P.V., Greene W.M.et al. The impact of high-. k gate dielectrics and metal gate electrodes on sub-100 nm MOSFET's IEEE Trans. ED. 46(7):1999;1537-1543.