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Volumn , Issue , 2003, Pages 732-737

Time domain multiplexed TAM: Implementation and comparison

Author keywords

Embedded core testing; Optimal test time; SoC testing; Test Access Mechanism (TAM); Time domain multiplexed TAM

Indexed keywords

EMBEDDED CORE TESTING; SOC TESTING; TEST ACCESS MECHANISM; TEST TIME; TIME DOMAIN;

EID: 0348129793     PISSN: 15301591     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DATE.2003.1253694     Document Type: Conference Paper
Times cited : (9)

References (11)
  • 3
    • 0035701269 scopus 로고    scopus 로고
    • Design of an optimal test access architecture using genetic algorithm
    • Z. Ebadi and A. Ivanov. Design of an optimal test access architecture using genetic algorithm. In Proc. of Asian Test Symposium, pages 205-210, 2001
    • (2001) Proc. of Asian Test Symposium , pp. 205-210
    • Ebadi, Z.1    Ivanov, A.2
  • 4
    • 0031354471 scopus 로고    scopus 로고
    • A low overhead design for testability and test generation technique for core-based systems
    • I. Ghosh, N. Jha, and S. Dey. A low overhead design for testability and test generation technique for core-based systems. In Proc. of International Test Conference, pages 50-59, 1999
    • (1999) Proc. of International Test Conference , pp. 50-59
    • Ghosh, I.1    Jha, N.2    Dey, S.3
  • 7
    • 0031361926 scopus 로고    scopus 로고
    • An IEEE 1149.1 based test access architecture for ic with embedded cores
    • L.Whetsel. An IEEE 1149.1 based test access architecture for ic with embedded cores. In Proc. of International Test Conference, pages 69-78, 1997
    • (1997) Proc. of International Test Conference , pp. 69-78
    • Whetsel, L.1
  • 8
    • 0032320505 scopus 로고    scopus 로고
    • A structures and scalable mechanism for test access to embedded reusable cores
    • E. Marinissen. A structures and scalable mechanism for test access to embedded reusable cores. In Proc. of International Test Conference, pages 284-293, 1998
    • (1998) Proc. of International Test Conference , pp. 284-293
    • Marinissen, E.1
  • 9
    • 0011840160 scopus 로고    scopus 로고
    • A packet switching communication-based test access mechanism for system chips
    • M. Nahvi and A. Ivanov. A packet switching communication-based test access mechanism for system chips. In Proc. of European Test Workshop, pages 81-86, 2001
    • (2001) Proc. of European Test Workshop , pp. 81-86
    • Nahvi, M.1    Ivanov, A.2
  • 11
    • 0033346855 scopus 로고    scopus 로고
    • Addressable test ports: An approach to testing embedded cores
    • L. Whetsel. Addressable test ports: An approach to testing embedded cores. In Proc. of International Test Conference, pages 1055-1064, 1999
    • (1999) Proc. of International Test Conference , pp. 1055-1064
    • Whetsel, L.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.