HD2BIST: a hierarchical framework for BIST scheduling, data patterns delivering and diagnosis in SoCs

IEEE International Test Conference (TC)

Volumn , Issue , 2000, Pages 892-901

  Benso, Alfredo ^a   Chiusano, Silvia ^a   Di Carlo, Stefano ^a   Prinetto, Paolo ^a   Ricciato, Fabio ^a   Spadari, Maurizio ^a   Zorian, Yervant ^a  

^a POLITECNICO DI TORINO   (Italy)

Author keywords

[No Author keywords available]

Indexed keywords

DESIGN FOR TESTABILITY; INTEGRATED CIRCUIT LAYOUT; INTEGRATED CIRCUIT TESTING; LOGIC CIRCUITS; LOGIC GATES; LOGIC PROGRAMMING; MICROPROCESSOR CHIPS; RANDOM ACCESS STORAGE;

DESIGN FOR REUSABILITY; SYSTEM-ON-A-CHIP; TEST ACCESS METHOD; TEST PATTERN GENERATOR;

BUILT-IN SELF TEST;

EID: 0034484423     PISSN: 10893539     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (8)