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Volumn 2003-January, Issue , 2003, Pages 293-298

An embedded autonomous scan-based results analyzer (EARA) for SoC cores

Author keywords

Testing; Very large scale integration

Indexed keywords

INTEGRATION TESTING; PROGRAMMABLE LOGIC CONTROLLERS; TESTING; VLSI CIRCUITS;

EID: 3142512933     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/VTEST.2003.1197666     Document Type: Conference Paper
Times cited : (3)

References (13)
  • 4
    • 84882876982 scopus 로고    scopus 로고
    • LogicVision. http://www.logicvision.com.
    • LogicVision
  • 6
    • 0034289979 scopus 로고    scopus 로고
    • Deterministic Built-in Test Pattern Generation for High-Performance Circuits Using Twisted-Ring Counters
    • October
    • K. Chakrabarty, B. T. Murray, and V. Iyengar, "Deterministic Built-in Test Pattern Generation for High-Performance Circuits Using Twisted-Ring Counters", IEEE Trans. On VLSI Systems, Vol. 8, No. 5, October 2000, pp. 633-636.
    • (2000) IEEE Trans. on VLSI Systems , vol.8 , Issue.5 , pp. 633-636
    • Chakrabarty, K.1    Murray, B.T.2    Iyengar, V.3
  • 11
    • 0011840160 scopus 로고    scopus 로고
    • A Packet Switching Communication-Based Test Access Mechanism for System Chips
    • M. Nahvi, A. Ivanov, "A Packet Switching Communication-Based Test Access Mechanism for System Chips", Proc. IEEE European Test Workshop, 2001, pp. 81-86.
    • Proc. IEEE European Test Workshop, 2001 , pp. 81-86
    • Nahvi, M.1    Ivanov, A.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.