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Volumn , Issue , 2002, Pages 1176-1183

Dedicated autonomous scan-based testing (DAST) for embedded cores

Author keywords

[No Author keywords available]

Indexed keywords

AUTOMATIC TESTING; BENCHMARKING; DATA REDUCTION; DIGITAL INTEGRATED CIRCUITS; EMBEDDED SYSTEMS; MICROPROCESSOR CHIPS; RESOURCE ALLOCATION; SCANNING; SEQUENTIAL CIRCUITS;

EID: 0036446466     PISSN: 10893539     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper
Times cited : (3)

References (16)
  • 2
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    • Test and test equipment
    • The International Technology Roadmap for Semiconductors
    • The International Technology Roadmap for Semiconductors, "Test and Test Equipment", 2001, http://public.itrs.net/.
    • (2001)
  • 4
    • 0003731578 scopus 로고    scopus 로고
    • Design for at-speed test, diagnosis, and measurement
    • Kluwer Academic Publishers
    • B. Nadeau-Dostie, "Design For At-speed Test, Diagnosis, and Measurement", Kluwer Academic Publishers, 2000.
    • (2000)
    • Nadeau-Dostie, B.1
  • 5
    • 0011874074 scopus 로고    scopus 로고
    • LogicVision
    • LogicVision, http://www.logicvision/com.
  • 6
    • 0003906698 scopus 로고    scopus 로고
    • Essentials of electronic testing, for digital, memory & mixed-signal VLSI circuits
    • Kluwer Academic Publishers, 2000, ISBN 0-7923-799-1-8
    • M. L. Bushnell, V. D. Agrawal, "Essentials of Electronic Testing, for Digital, Memory & Mixed-signal VLSI Circuits", Kluwer Academic Publishers, 2000, ISBN 0-7923-799-1-8.
    • (2000)
    • Bushnell, M.L.1    Agrawal, V.D.2
  • 7
    • 0033307908 scopus 로고    scopus 로고
    • Testing a system-on-a-chip with embedded microprocessors
    • R. Rajsuman, "Testing a System-on-a-Chip with Embedded Microprocessors", Proc. IEEE ITC, 1999. pp. 499-508.
    • Proc. IEEE ITC, 1999 , pp. 499-508
    • Rajsuman, R.1
  • 8
    • 0033329245 scopus 로고    scopus 로고
    • A low overhead design for testability and test generation technique for core-based systems-on-a-chip
    • November
    • I. Gosh, N. K. Jha, S. Dey, "A Low Overhead Design for Testability and Test Generation Technique for Core-based Systems-on-a-Chip", IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, Vol. 18, No. 11, November 1999, pp. 1661-1676.
    • (1999) IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems , vol.18 , Issue.11 , pp. 1661-1676
    • Gosh, I.1    Jha, N.K.2    Dey, S.3
  • 10
    • 0003522570 scopus 로고    scopus 로고
    • Embedded deterministic test-DFT technology for low-cost iC manufacturing test
    • Mentor Graphics Corporation
    • Mentor Graphics Corporation, "Embedded Deterministic Test-DFT Technology for Low-Cost IC Manufacturing Test", http://www/mentor.com/dft, 2001.
    • (2001)
  • 11
  • 12
    • 0011798797 scopus 로고    scopus 로고
    • ITC99 Benchmarks Home Page
    • ITC99 Benchmarks Home Page: http://www.cerc.utexas.edu/itc99-benchmarks/bench.html.
  • 13
    • 0011843446 scopus 로고    scopus 로고
    • ITC'02 Benchmarks Home Page
    • ITC'02 Benchmarks Home Page: http;//www.extra.research.philips.com/itc02socbenchm/.
  • 14
    • 0011878765 scopus 로고    scopus 로고
    • IEEE P1500 Standard for Embedded Core Test (SECT)
    • IEEE P1500 Standard for Embedded Core Test (SECT), http://grouper.ieee.org/groups/1500.
  • 15
    • 0011840160 scopus 로고    scopus 로고
    • A packet switching communication-based test access mechanism for system chips
    • M. Nahvi, A. Ivanov, "A Packet Switching Communication-Based Test Access Mechanism for System Chips", Proc. IEEE European Test Workshop, 2001, pp. 81-86.
    • Proc. IEEE European Test Workshop, 2001 , pp. 81-86
    • Nahvi, M.1    Ivanov, A.2
  • 16
    • 0034289979 scopus 로고    scopus 로고
    • Deterministic built-in test pattern generation for high-performance circuits using twisted-ring counters
    • October
    • K. Chakrabarty, B. T. Murray, and V. Iyengar, "Deterministic Built-in Test Pattern Generation for High-Performance Circuits Using Twisted-Ring Counters", IEEE Trans. On VLSI Systems, Vol. 8, No. 5, October 2000, pp. 633-636.
    • (2000) IEEE Trans. on VLSI Systems , vol.8 , Issue.5 , pp. 633-636
    • Chakrabarty, K.1    Murray, B.T.2    Iyengar, V.3


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.