CMOS technology for MS/RF SoC

IEEE Transactions on Electron Devices

Volumn 50, Issue 3, 2003, Pages 557-566

  Diaz, Carlos H ^a   Tang, Denny D ^a   Sun, Jack Yuan Chen ^a  

^a TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY   (Taiwan)

Author keywords

(MS RF); 1 f noise; Analog; Analog CMOS; CMOS RF; CMOS system on chip (SoC); CMOS technology; Device isolation; Gate dielectric; Gate dielectric direct tunneling; Gate patterning; Integrated capacitors; Integrated inductors; Integrated resistors; Line edge roughness (LER); Matching; Mechanical stress in MOS devices; Mixed signal (MS); Mixed signal radio frequency; Noise isolation; Passive elements; Source drain engineering; System on chip (SoC)

Indexed keywords

CAPACITANCE; DIELECTRIC FILMS; ELECTRONICS PACKAGING; GATES (TRANSISTOR); INTEGRATED CIRCUIT LAYOUT; LEAKAGE CURRENTS; MOSFET DEVICES; SIGNAL TO NOISE RATIO; STATIC RANDOM ACCESS STORAGE; THRESHOLD VOLTAGE;

DEVICE ISOLATION; GATE DIELECTRIC DIRECT TUNNELING; GATE PATTERNING; LINE-EDGE ROUGHNESS; MIXED SIGNAL-RADIO FREQUENCY SEGMENT; SYSTEM-ON-A-CHIP;

CMOS INTEGRATED CIRCUITS;

EID: 0038236509     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/TED.2003.810472     Document Type: Article

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