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Volumn 33, Issue 12, 1998, Pages 2035-2041

Fractal Capacitors

(5)  Samavati, Hirad a,b,f,g,h   Hajimiri, Ali b,c,f,i,j,k,l   Shahani, Arvin R b,m,n   Nasserbakht, Gitty N b,d,e,i,o,p,q   Lee, Thomas H a,b,r,s,t  


Author keywords

[No Author keywords available]

Indexed keywords

CAPACITANCE; COMPUTATIONAL GEOMETRY; COMPUTER AIDED DESIGN; ELECTRIC FIELDS; INTEGRATED CIRCUIT LAYOUT;

EID: 0032316465     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/4.735545     Document Type: Article
Times cited : (178)

References (8)
  • 2
    • 84889210640 scopus 로고    scopus 로고
    • "High capacitance structures in a semiconductor device," U.S. Patent 5 208 725, May 1993
    • O. E. Akcasu, "High capacitance structures in a semiconductor device," U.S. Patent 5 208 725, May 1993.
    • Akcasu, O.E.1
  • 3
    • 0029547914 scopus 로고
    • Interconnect scaling - The real limiter to high performance ULSI
    • M. Bohr, "Interconnect scaling - The real limiter to high performance ULSI," in Int. Electron Devices Meeting Tech. Dig., 1995, pp. 241-244.
    • (1995) Int. Electron Devices Meeting Tech. Dig. , pp. 241-244
    • Bohr, M.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.