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Volumn , Issue , 2000, Pages

DSP & analog soc integration in the Internet Era

Author keywords

[No Author keywords available]

Indexed keywords

APPLICATION SPECIFIC INTEGRATED CIRCUITS; INTEGRATION; INTERNET; PERSONAL COMPUTERS; PROGRAM PROCESSORS; PROGRAMMABLE LOGIC CONTROLLERS;

EID: 84955167388     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ETS.2000.916520     Document Type: Conference Paper
Times cited : (7)

References (6)
  • 1
    • 0002666776 scopus 로고    scopus 로고
    • Analog broadband communication circuits in pure digital deep sub-micron CMOS
    • 448, Feb.
    • Klaas Bult, "Analog Broadband Communication Circuits in Pure Digital Deep Sub-Micron CMOS," ISSCC99 Digital Tech Papers, pp. 76-77, 448, Feb. 1999.
    • (1999) ISSCC99 Digital Tech Papers , pp. 76-77
    • Bult, K.1
  • 2
    • 0033325117 scopus 로고    scopus 로고
    • Device issues in the integration of analog RF functions in deep submicron digital CMOS
    • Washington DC, Dec.
    • Dennis Buss, "Device Issues in the Integration of Analog RF Functions in Deep Submicron Digital CMOS", IEDM, Washington DC, pp 423-426. Dec. 1999.
    • (1999) IEDM , pp. 423-426
    • Buss, D.1
  • 3
    • 0033280393 scopus 로고    scopus 로고
    • Transistor design issues in integrating analog functions with high performance digital CMOS
    • Amitava Chatterjee, et al, "Transistor Design Issues in Integrating Analog Functions with High Performance Digital CMOS," 1999 Symposium on VLSI, VLSI Tech., pp. 147-148.
    • 1999 Symposium on VLSI, VLSI Tech. , pp. 147-148
    • Chatterjee, A.1
  • 4
    • 84893789080 scopus 로고    scopus 로고
    • Design of spiral inductors on silicon substrates with a fast simulator
    • The Hague, The Netherlands, September
    • J. Lee, A. Kral, A.A. Abidi, and N.G. Alexopoulos, "Design of Spiral Inductors on Silicon Substrates with a Fast Simulator," European Solid-state Circuits Conf., The Hague, The Netherlands, pp. 328-331, September 1998.
    • (1998) European Solid-state Circuits Conf. , pp. 328-331
    • Lee, J.1    Kral, A.2    Abidi, A.A.3    Alexopoulos, N.G.4
  • 5
    • 84955061537 scopus 로고    scopus 로고
    • Predictive BSIM3 modeling for the 0.15-0.18μ CMOS technology node; A process DOE based approach
    • Washington DC, pp. 353-356, Dec.
    • K. Vasanth, et al, "Predictive BSIM3 Modeling for the 0.15-0.18μ CMOS Technology Node; A Process DOE Based Approach," IEDM, VLSI, VLSI Tech., pp. 147-148. Washington DC, pp. 353-356, Dec. 1999.
    • (1999) IEDM, VLSI, VLSI Tech. , pp. 147-148
    • Vasanth, K.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.