Future perspective and scaling down roadmap for RF CMOS

Digest of Technical Papers - Symposium on VLSI Technology

Volumn , Issue , 1999, Pages 163-164

  Morifuji, E ^a   Momose, H S ^a   Ohguro, T ^a   Yoshitomi, T ^a   Kimijima, H ^a   Matsuoka, F ^a   Kinugawa, M ^a   Katsumata, Y ^a   Iwai, H ^a  

^a TOSHIBA CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

CALCULATIONS; CMOS INTEGRATED CIRCUITS; COMPUTER SIMULATION; ELECTRIC CURRENTS; ELECTRIC RESISTANCE; EQUIVALENT CIRCUITS; GATES (TRANSISTOR); LINEAR INTEGRATED CIRCUITS; MOS DEVICES; OPTIMIZATION;

FINGER LENGTH; GATE LENGTH; GATE WIDTH; MIXED SIGNAL CIRCUIT; SCALING DOWN;

INTEGRATED CIRCUIT MANUFACTURE;

EID: 0033280627     PISSN: 07431562     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (4)