Application-dependent scaling tradeoffs and optimization in the SoC Era

Proceedings of the Custom Integrated Circuits Conference

Volumn , Issue , 2002, Pages 475-478

  Díaz, Carlos H ^a   Chang, Mi Chang ^a   Ong, T C ^a   Sun, Jack ^a  

^a TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY   (Taiwan)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; DIELECTRIC MATERIALS; ELECTRON TUNNELING; INTEGRATED CIRCUIT LAYOUT; OPTIMIZATION; STRESSES; TRANSISTORS;

GATE DIELECTRICS; MECHANICAL STRESSES;

SURFACE MOUNT TECHNOLOGY;

EID: 0036046053     PISSN: 08865930     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (10)

1. Hole mobility improvement in SOI and bulk silicon using local strain
2. A 0.13 um CMOS technology with 193 nm lithography and Cu/Low-k for high performance applications
3. NMOS drive current reduction caused by transistor layout and trench isolation induced stress
4. A 0.15 μm CMOS foundry technology with 0.1 μm devices for high performance applications
5. Scaling challenges and device design requirements for high-performance sub-50nm gate-length planar transistors
6. Device scaling limits for Si MOSFETs and their application dependencies
7. Modeling line edge roughness effects in sub 100nm gate length devices
8. An experimentally validated analytical model for gate line-edge roughness (LER) effects on technology scaling
9. Scaling-induced reductions in CMOS reliability margins and the escalating need for increased design-for reliability efforts