Effectiveness of adaptive supply voltage and body bias for reducing impact of parameter variations in low power and high performance microprocessors

IEEE Symposium on VLSI Circuits, Digest of Technical Papers

Volumn , Issue CIRCUITS SYMP., 2002, Pages 310-311

  Tschanz, James ^a   Narendra, Siva ^a   Nair, Raj ^a   De, Vivek ^a  

^a INTEL CORPORATION   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CAPACITANCE; CMOS INTEGRATED CIRCUITS; ELECTRIC POWER SUPPLIES TO APPARATUS; FREQUENCIES; LEAKAGE CURRENTS; MICROPROCESSOR CHIPS;

ADAPTIVE SUPPLY VOLTAGE; BODY BIAS; CIRCUIT BLOCKS; WITHIN-DIE;

LOGIC DESIGN;

EID: 0242611611     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (3)

1. M. Miyazaki et. al., 2000 ISSCC, pp. 420-421.
2. J. Tschanz et. al., 2002 ISSCC, paper 25.7.
3. A. Keshavarzi et. al., 2001 ISLPED, pp. 207-212.