VLSI module placement based on rectangle-packing by the sequence-pair

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 15, Issue 12, 1996, Pages 1518-1524

  Murata, Hiroshi ^a   Fujiyoshi, Kunihiro ^a   Nakatake, Shigetoshi ^a   Kajitani, Yoji ^a  

^a JAPAN ADVANCED INSTITUTE OF SCIENCE AND TECHNOLOGY   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

COMBINATORIAL MATHEMATICS; COMPUTATIONAL COMPLEXITY; DECISION THEORY; ELECTRIC WIRING; FINITE AUTOMATA; INTEGRATED CIRCUIT LAYOUT; OPTIMIZATION; POLYNOMIALS; SIMULATED ANNEALING;

COMBINATORIAL OPTIMIZATION PROBLEM; CONVENTIONAL WIRING AREA ESTIMATION METHOD;

VLSI CIRCUITS;

EID: 0030378255     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/43.552084     Document Type: Article

References (13)

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