Precedence-based, preemptive, and power-constrained test scheduling for system-on-a-chip

Proceedings of the IEEE VLSI Test Symposium

Volumn , Issue , 2001, Pages 368-374

  Iyengar, V ^a   Chakrabarty, K ^a  

^a Duke University   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; BUILT-IN SELF TEST; CONSTRAINT THEORY; INTEGRATED CIRCUIT LAYOUT; LINEAR PROGRAMMING; MICROPROCESSOR CHIPS; POLYNOMIALS;

PRECEDENCE CONSTRAINT; PREEMPTIVE TEST SCHEDULING; RANDOM-RESISTANT FAULT; SYSTEM-ON-A-CHIP; TEST SCHEDULING;

INTEGRATED CIRCUIT TESTING;

EID: 0034995151     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (15)

1. Test scheduling for core-based systems using mixed-integer linear programming
2. Design of system-on-a-chip test access architectures under place-and-route and power constraints
3. Optimal test access architectures for system-on-a-chip
4. Test access methodology for system-on-chip testing
5. Scheduling tests for VLSI systems under power constraints
6. Open shop scheduling to minimize finish time
7. Defect-oriented test scheduling
8. Test protocol scheduling for embedded-core based system ICs
9. The role of test protocols in testing embedded-core-based system ICs
10. List scheduling and tree growing technique in power-constrained block-test scheduling
11. A novel test methodology for core-based system LSIs and a testing time minimization problem
12. Testing embedded-core-based system chips