Automatic test generation algorithms for analogue circuits

IEE Proceedings: Circuits, Devices and Systems

Volumn 143, Issue 6, 1996, Pages 366-373

  Soma, M ^a  

^a UNIVERSITY OF WASHINGTON   (United States)

Author keywords

Analogue circuits; Automatic lest generation

Indexed keywords

ALGORITHMS; AUTOMATIC TESTING; MIXER CIRCUITS;

ANALOGUE CIRCUITS; AUTOMATIC TEST GENERATION ALGORITHMS; BUILT IN SELF TEST (BIST);

INTEGRATED CIRCUIT TESTING;

EID: 0030378967     PISSN: 13502409     EISSN: None     Source Type: Journal    
DOI: 10.1049/ip-cds:19960898     Document Type: Article

References (59)

1. SOMA, M.: 'Fault coverage of DC parametric tests for embedded analog amplifiers'. Presented at IEEE Int. Test Conf, 1993, Baltimore, MD
2. 'Semiconductor industry technology workshop conclusions'. Presented at Semiconductor Industry Technology Workshop, 1993
3. BISHOP, A.J., and IVANOV, A.: 'On the testability of CMOS feedback amplifiers'. Presented at Int. Workshop on Defect and Fault Tolerance in VLSI Systems, 1994
4. WEY, C.L., and SAEKS, R.: 'On the implementation of an analog ATPG: The linear case', IEEE Trans. Instrum. Meas., 1985, 34, pp. 442149
5. LEENAERTS, D.M.W., and VAN SPAANDONK, J.: 'A contribution to testing of analog integrated circuits in the DC domain'. Presented at European Test Conference, 1993, Rotterdam, The Netherlands
6. WEY, C.-L., KRISHNAN, S., and SAHLI, S.: 'Test generation and concurrent error detection in current-mode AID converters'. IEEE Trans. CAD Integr. Circuits Syst., 1995, 14, pp. 1291-1298
7. ZWEMSTRA, T., AND SEUREN, G.P.H.: 'Analog test signal generation on a digital tester'. Presented at European Test Conference, Rotterdam, The Netherlands, 1993
8. WEI, T., WONG, M.W.T., and LEE, Y.S.: 'Analogue elementlevel fault diagnosis based on large change sensitivity computation in the frequency domain'. Presented at IEEE Int. Mixed Signal Testing Workshop, 1996, Quebec City, Canada
9. RAMADOSS, R., and BUSHNELL, M.L.: 'Test generation for mixed-signal devices using signal flow graphs'. Presented at IEEE Int. Conf. on VLSI Design, 1996, Bangalore, India
10. BALIVADA, A., CHEN, J., and ABRAHAM, J.A.: 'Efficient testing of linear analog circuits'. Presented at IEEE Int. Mixed Signal Testing Workshop, 1995, Grenoble, France
11. BALIVADA, A., CHEN, J., and ABRAHAM, J.A.: 'Analogue testing with time response parameters', IEEE Des. Test Comput., 1996, pp. 18-25
12. TSAI, S.-J.: 'Test vector generation for linear analog devices'. Presented at IEEE Int. Test Conf., 1991, Nashville, TN
13. MIR, S., LUBASZEWSKI, M., KOLARIK, V., and COURTOIS, B.: 'Optimal ATPG for analog built-in self-test and fault diagnosis'. Presented at IEEE Int. Mixed Signal Testing Workshop, 1995, Grenoble, France
14. LIU, R.-W.: 'Selected papers on analog fault diagnosis', m 'Advances in circuits and systems' (IEEE Press, New York, 1987), p. 143
15. HAMIDA, N.B., and KAMINSKA, B.: 'Analogue circuit testing based on sensitivity computation and new circuit modeling'. Presented at IEEE Int. Test Conf., 1993, Baltimore, MD
16. NAGI, N., CHATTERJEE, A., BALIVADA, A., and ABRAHAM, J.A.: 'Fault-based automatic test generator for linear analog circuits'. Presented at IEEE Int. Conf. on Computer-Aided Design, 1993, Santa Clara, CA
17. CORSI, F., CHIARANTONI, M., LORUSSO, R., and MARZOCCA, C.: 'A fault signature approach to analog devices testing'. Presented at European Test Conference, 1993, Rotterdam, The Netherlands
18. SCHREIBER, H.H.: 'Fault dictionary based upon stimulus design', IEEE Trans. Circuits Syst., 1979, 26
19. ABDERRAHMAN, A., CERNY, E., and KAMINSKA, B.: 'Effective test generation for analog circuits'. Presented at IEEE Int. Mixed Signal Testing Workshop, 1995, Grenoble, France
20. SLAMANI, S., and KAMINSKA, B.: 'Multifrequency testability analysis for analog circuits'. Presented at IEEE VLSI Test Symp., 1994, Princeton, NJ
21. HAMIDA, N.B., and KAMINSKA, B.: 'Multiple fault analog circuit testing by sensitivity analysis', Analog Intcgr. Circuits Signal. Process., 1993, 4, pp. 231-243
22. FELT, E., and SANGIOVANNI-VINCENTELLI, A.L.: 'Testing of analog systems using behavioral models and optimal experimental design techniques'. Presented at IEEE Int. Conf. on Computer-Aided Design, 1994, San Jose, CA
23. SAAB, K., MARCHE, D., KAMINSKA, B., HAMIDA, N.B., and QUESNEL, G.: 'LIMSoft:Automated tool for sensitivity analysis used for test vector generation'. Presented at IEEE Int. Mixed Signal Testing Workshop, 1995, Grenoble, France
24. HAMIDA, N.B., SAAB, K., MARCHE, D., KAMINSKA, B., and QUESNEL, G.: 'LIMSoft: Automated tool for design and test integration'. Presented at IEEE Int. Mixed Signal Testing Workshop, 1996, Quebec City, Canada
25. MARLETT, M.J., and ABRAHAM, J.A.: 'DCJTAP - An iterative analog circuit test generation program for generating DC single pattern tests'. Presented at IEEE Int. Test Conf., 1988, Washington, DC
26. DEVARAYANADURG, G., and SOMA, M.: 'Analytical fault modeling and static test generation for analog ICS'. Presented at IEEE Int. Conf. on Computer-Aided Design, 1994, San Jose, CA
27. DEVARAYANADURG, G., and SOMA, M.: 'Dynamic test signal design for analog ICs'. Presented at IEEE Int. Conf. on Computer-Aided Design, 1995, (San Jose, CA)
28. DDX test strategies in analog and mixed signal ICs'. Presented at IEEE Int. Mixed Signal Testing Workshop, 1995, Grenoble, France
29. GIELEN, G., WANG, Z., and SANSEN, W.: 'Fault detection and input stimulus determination for the testing of analog integrated circuits based on power-supply current monitoring'. Presented at IEEE Int. Conf. on Computer-Aided Design, 1994, San Jose, CA
30. DD pulse response testing of analog and digital CMOS circuits'. Presented at IEEE Int. Test Conf., 1993, Washington, DC
31. MIURA, Y.: 'Real-time current testing for A/D converters', IEEE Des. Test Compiit., 1996, pp. 34-41
32. SOMAYAJULA, S.S., SANCHEZ-SINENCIO, E., and PINEDA DE GYVEZ, J.: 'A power supply ramping and current measurement based technique for analog fault diagnosis. Presented at IEEE VLSI Test Symp., 1994, Atlantic City, NJ
33. PAN, C.-Y., and CHENG, K.-T.: 'Pseudo-random testing and signature analysis for mixed-signal circuits'. Presented at IEEE Int. Conf. on VLSI Design, 1995, San Jose, CA
34. MILOR, L., and VISVANATHAN, V.: 'Detection of catastrophic faults in analog integrated circuits', IEEE Trans. CAD Integr. Circuits Syst., 1989, 8, pp. 114-130
35. MILOR, L., and SANGIOVANNI-VINCENTELLI, A.L.: 'Optimal test set design for analog circuits'. Presented at IEEE Int. Conf. on Computer-Aided Design, 1990, Santa Clara, CA
36. MILOR, L., and SANGIOVANNI-VINCENTELLI, A.L.: 'Minimising production test time to detect faults in analog circuits', IEEE Trans. CAD Integrated Circuits Syst., 1994,13, pp. 796-813
37. SOUDERS, T.M., and STENBAKKEN, G.N.: 'Cutting the high cost of testing", Spectrum, 1991, pp. 48-51
38. HUSS, S.D., and GYURCSIK, R.S.: 'Optimal ordering of analog integrated circuit tests to minimise test time'. Presented at IEEE Design Automation Conf., 1991
39. LINDERMEIR, W.M., GRAEB, H.E., and ANTREICH, K.J.: 'Design-based analog testing by characteristic observation inference'. Presented at IEEE Int. Conf. on Computer-Aided Design, 1995, San Jose, CA
40. KAAL, V., and KERKHOFF, H.: 'On the optimisation and optimal selection for analog/mixed-sianal macros'. Presented at IEEE Int. Mixed Signal Testing Workshop, 1996, Quebec City, Canada
41. HUERTAS, J.L., RUEDA, A., and VAZQUEZ, D.: 'Design for testability techniques applicable to analog circuits'. Presented at European Test Conference, 1993, Rotterdam, Holland
42. HUERTAS, J.L., RUEDA, A., and VAZQUEZ, D.: 'Improving the testability of switched capacitor filters', Analogue Int. Circuits Sig. Process., 1993, 4, pp. 199-213
43. HUERTAS, J.L., RUEDA, A., and VAZQUEZ, D.: 'Testable switched-capacitor filters', IEEE J. Solid State Circuits, 1993, 28, pp. 719-724
44. VAZQUEZ, D., RUEDA, A., and HUERTAS, J.L.: 'A new strategy for testing analog filters'. Presented at IEEE VLSI Test Symp., 1994, Atlantic City, NJ
45. SONIA, M.: 'A design-for-test methodology for active analog filters'. Presented at IEEE Int. Test Conf., 1990, Washington, DC
46. SOMA, M., and KOLARIK, V.: 'A design-for-test technique for switched-capacitor filters'. Presented at IEEE VLSI Test Symp., 1994, Cherry Hill, NJ
47. BRATT, A.H., HARVEY, R.J., DOREY, A.P., and RICHARDSON, A.M.D.: 'Design-for-test structure to facilitate test vector application with low performance loss in non-test mode', Electron. Lett., 1993, 29, pp. 1438-1440
48. VAZQUEZ, D., RUEDA, A., HUERTAS, J.-L., and RICHARDSON, A.M.D.: 'Practical DFT strategy for fault diagnosis in active analog filters', Electron. Lett., 1995, 31, pp. 1221-1222
49. VAZQUEZ, D., HUERTAS, J.-L., and RUEDA, A.: 'Reducing the impact of DFT on the performance of analog integrated circuits: Improved sw-opamp design'. Presented at IEEE VLSI Test Symp., 1996, Princeton, NJ
50. VAZQUEZ, D., RUEDA, A., and HUERTAS, J.-L.: 'Fully differential sw-opamp for testing analog embedded modules'. Presented at IEEE Int. Mixed Signal Testing Workshop, 1996, Quebec City, Canada
51. TONER, M.F., and ROBERTS, G.W.: 'A BIST scheme for a SNR, gain tracking, and frequency response test of a sigma-delta ADC', IEEE Trans. Circuits Syst. Il, Analog Digit. Signal Process., 1995, 42, pp. 1-15
52. WEY, C.: 'Built-in self-test (BIST) structure for analog circuit fault diagnosis', IEEE Trans. lustrum. Meas., 1990, 39, pp. 517-521
53. WURTZ, L.T.: 'Built-in self-test structure for mixed-mode cir. cuits', IEEE Trans. lustrum. Meas., 1993, 42, pp. 25-29
54. SOMA, M.: 'Structure and concepts for current-based analog scan'. Presented at IEEE Custom Integrated Circuits Conf., 1995, San Jose, CA
55. WEY, C.-L., and KRISHNAN, S.: 'Built-in self-test (BIST) structures for analog circuit fault diagnosis with current test data', IEEE Trans. Instrum. Meas., 1992, 41, pp. 535-539
56. NEJAD, M.S., SEBAA, L.L., LADICK, A., and KUO, H.: 'Analog built-in self-test'. Presented at IEEE VLSI Test Symp., 1994, Philadelphia, PA
57. RZESZUT, J., and KAMINSKA, B.: 'A built-in self-test method for digital-to- analog converter'. Presented at New Frontiers in Test Workshop, 1993, Montreal, Canada
58. ARABI, K., KAMINSKA, B., and RZESZUT, J.: 'A new builtin self-test approach for digital-to-analog and analog-to-digital converters'. Presented at IEEE Int. Conf. on Computer-Aided Design, 1994, San Jose, CA
59. ARABI, K., and KAMINSKA, B.: 'Oscillation-test strategy for analog and mixed-signal integrated circuits'. Presented at IEEE VLSI Test Symp., 1996, Princeton, NJ