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Volumn 42, Issue 1, 1995, Pages 1-15

A BIST Scheme for a SNR, Gain Tracking, and Frequency Response Test of a Sigma-Delta ADC

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRONIC EQUIPMENT TESTING; FREQUENCY RESPONSE; INTEGRATED CIRCUIT MANUFACTURE; PROGRAM DIAGNOSTICS; SIGNAL TO NOISE RATIO; VLSI CIRCUITS;

EID: 0029209323     PISSN: 10577130     EISSN: None     Source Type: Journal    
DOI: 10.1109/82.363546     Document Type: Article
Times cited : (91)

References (18)
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    • A BIST scheme for an SNR test of a Sigma-Delta ADC
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    • M. F. Toner and G. W. Roberts, “A BIST scheme for an SNR test of a Sigma-Delta ADC,” in 1993 Proc. Int. Test Conf., Baltimore, MD, Oct. 1993, pp. 805-814.
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    • Toner, M.F.1    Roberts, G.W.2
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* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.