Test Generation and Concurrent Error Detection in Current-Mode A/D Converters

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 14, Issue 10, 1995, Pages 1291-1298

  Sahli, Sondes ^a  

^a MICHIGAN STATE UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

DIGITAL INTEGRATED CIRCUITS; ELECTRIC CONVERTERS; ERROR DETECTION; MATHEMATICAL MODELS; MOS DEVICES; SWITCHING; VLSI CIRCUITS;

ANALOG WINDOW COMPARATOR; CONCURRENT ERROR DETECTION; CURRENT-MODE ANALOG TO DIGITAL CONVERTERS; DIGITAL CLOCK SIGNALS; SELF-CALIBRATING TECHNIQUES; SOPHISTICATED TESTING SCHEMES; TEST GENERATION;

ANALOG TO DIGITAL CONVERSION;

EID: 0029391673     PISSN: 02780070     EISSN: 19374151     Source Type: Journal    
DOI: 10.1109/43.466344     Document Type: Article

References (17)

1. Y. P. Tisividis, “Analog MOS integrated circuits—Certain new ideas, trends, and obstacles,” IEEE J. Solid-State Circuits, vol. SC-22, pp. 317–321, June 1987.
2. R. Poujois, B. Baylac, D. Barbier and J. M. Ittel, “Low-level MOS transistor amplifier using storage elements,” in IEEE ISSCC Dig. Tech. Papers, 1973, pp. 152–153.
3. Y. P. Tisvidis, M. Banu and J. F. Khoury, “Continuous-time MOSFET-C Filters in VLSI,” IEEE J. Solid-State Circuits, vol. SC-21, pp. 15–30, Feb. 1986.
4. H. T. Yung and K. S. Chao, “An error-compensation A/D conversion technique,” IEEE Trans. Circuits Syst., vol. 38, pp. 187–195, Feb. 1991.
5. Analog Devices, Analog-Digital Conversion Handbook. Englewood Cliffs, NJ: Prentice-Hall, 1986.
6. J. A. Abraham and V. K. Agarwal, “Test generation for digital systems,” in Fault-Tolerant Computing, Theory and Techniques, D. K. Pradhan, Ed. Englewood Cliffs, NJ: Prentice-Hall, 1986.
7. P. K. Lala, Fault Tolerant & Fault Testable Hardware Design. Englewood Cliffs, NJ: Prentice-Hall, 1985.
8. D. G. Nairn and C. S. Salama, “A ratio-independent algorithmic analog-to-digital converter combining current mode and dynamic techniques,” IEEE Trans. Circuits Syst., vol. 37, no. 3, pp. 319–325, Mar. 1990.
9. C. L. Wey, S. Krishnan and S. Sondes, “CMOS current copiers,” Dep. Elec. Eng., Michgan State University, East Lansing, Tech. Rep. 91-WKS015, Nov. 1991.
10. J. H. Patel and L. Y. Fung, “Concurrent error detection in ALU's by recomputing with shifted operands,” IEEE Trans. Comput., vol. C-31, no. 7, pp. 589–595, July 1982.
11. Y. H. Choi, S. H. Han, and M. Malek, “Fault diagnosis of reconfigurable systolic arrays,” in Proc. Int. Conf. Comput. Design: VLSI Comput. & Processors (ICCD'84), 1984, pp. 451–455.
12. R. K. Gulati and S. M. Reddy, “Concurrent error detection VLSI structures,” in Proc. Int. Conf. Comput. Design: VLSI Comput. & Processors (ICCD '86), 1986, pp. 488–491.
13. S.-W. Chan, S. S. Leung and C. L. Wey, “Systematic design strategy for concurrent error diagnosable iterative logic arrays,” in IEE Proc., Part E, Comput. Digital Techniques, Mar. 1988, vol. 135, no. 2, pp. 87–94.
14. S. -W. Chan and C. L. Wey, “The design of concurrent error diagnosable systolic arrays for band-matrix multiplication,” IEEE Trans. Computer-Aided Design, vol. CAD-7, no. 1, pp. 21–37, Jan. 1988.
15. D. A. Reynolds and G. Metze, “Fault detection capabilities of alternating logics,” IEEE Trans. Comput., vol. C-27, no. 12, pp. 1093–1098, Dec. 1978.
16. C. L. Wey, “Concurrent error detection in array dividers by alternating input data,” in Proc. Int. Conf. Comput. Design: VLSI Comput. & Processors (ICCD'91), Oct. 1991, pp. 114–117.
17. S. Sahli, “Test generation and concurrent error detection in current-mode A/D converters,” M.S. thesis, Dep. Elec. Eng., Michigan State Univ., East Lansing, May 1992.