Reducing the impact of DFT on the performance of analog integrated circuits: improved SW-OPAMP design

Proceedings of the IEEE VLSI Test Symposium

Volumn , Issue , 1996, Pages 42-47

  Vazquez, Diego ^a   Huertas, Jose L ^a   Rueda, Adoracion ^a  

^a UNIVERSITY OF SEVILLE   (Spain)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; CONTROLLABILITY; INTEGRATED CIRCUIT LAYOUT; LINEAR INTEGRATED CIRCUITS; OBSERVABILITY; PERFORMANCE;

ANALOG CIRCUITS TESTING; ANALOG INTEGRATED CIRCUITS; DESIGN FOR TESTABILITY; SW-OPAMP CONCEPT;

INTEGRATED CIRCUIT TESTING;

EID: 0029710664     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (16)