Current drive enhancement by using high-permittivity gate insulator in SOI MOSFET's and its limitation

IEEE Transactions on Electron Devices

Volumn 43, Issue 3, 1996, Pages 431-435

  Shimada, Hisayuki ^a   Ohmi, Tadahiro ^a  

^a TOHOKU UNIVERSITY   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

CAPACITANCE; CMOS INTEGRATED CIRCUITS; COMPUTER SIMULATION; ELECTRIC CURRENTS; ELECTRIC INSULATORS; ELECTRIC INVERTERS; ELECTRIC WAVEFORMS; GATES (TRANSISTOR); PERMITTIVITY; SEMICONDUCTOR DEVICE MODELS; SILICON ON INSULATOR TECHNOLOGY; TANTALUM COMPOUNDS;

CIRCUIT SIMULATOR; CMOS INVERTER; CURRENT DRIVE ENHANCEMENT; HIGH PERMITTIVITY GATE INSULATOR; PULSE WAVEFORMS; TWO DIMENSIONAL DEVICE SIMULATOR;

MOSFET DEVICES;

EID: 0030105752     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/16.485657     Document Type: Article

References (23)

1. K. Shimohigashi and K. Seki, I.ow-voltage UI.SI design, IEEE .1. Solid-Stale Circuits, vol. 28, no. 4, pp. 408-413, 1993.
2. T. Ohrai, Trends for future silicon technology, Jpn. J. Appl. Phys., vol. 33, no. 12B, pp. 6747-6755, 1994.
3. T. ühmi, S. Irnai, and T. Hashimoto, VLSI interconnects for ultra high speed signal propagation, in Proc. 5th Int. IEEE VLSI Multilevel Interconnection CanJ., pp. 261-267, 1988.
4. K. Kotani, T. Ohmi, S. Shimonishi, T. Migita, H. Komori, and T. Shibata, Self-aligned aluminum-gate MOSFET's having ultra-shallow junctions formed by 450° C furnace annealing, IEICE Trans. Electron., vol. E76-C, no. 4, pp. 541-547, 1993.
5. S. Veeraraghavan and J. G. Possum, Short-channel effects in SOI MOSFET's, IEEE Trans. Electron Devices, vol. 36, no. 3, pp. 522-528, 1989.
6. K. K. Young, Short-channel effect in fully depleted SOI MOSFET's, IEEE Trans. Electron Devices, vol. 36, no. 2, pp. 399-402, 1989.
7. J. C. Sturm, K. Tokunaga, and J.-P. Colinge, Increased drain saturation current in ultra-thin silicon-on-insulator (SOI) MOS transistors, IEEE Electron Device Lett., vol. 9, no. 9, pp. 46CM63, 1988.
8. M. Yoshimi, H. Hazama. M. Takahashi, S. Kambayashi, and H. Tango, Observation of mobility enhancement in ultra-thin SOI, Electron. Lett., vol. 24, no. 17, pp. 1078-1079, 1988.
9. J.-P. Colinge, Hot-electron effects in silicon-on-insulator n.-channel MOSFET's, IEEE Tram. Electron Devices, vol. ED-34, no. 10, pp. 2173-2177, 1987.
10. K. Yamaguchi, A mobility model for carriers in the MOS inversion layer, IEEE Trans. Electron Devices, vol. ED-30, no. 6, pp. 658-663, 1983.
11. H.-K. Lim, and J. G. Possum, Current-voltage characteristics of thinfilm SOI MOSFET's in strong inversion, IEEE Trans. Electron Devices, vol. ED-31, no. 4, pp. 401-108, 1984.
12. D. J. Wouters, J.-P. Colinge, and H. E. Maes, Subthreshold slop in thin-film SOI MOSFET's, IEEE Trans. Electron Devices, vol. ED-37, no. 9, pp. 2022-2033. 1990.
13. H.-O. Joachim, Y. Yamaguchi, K. Ishikawa, N. Kotani. T. Nishimura, and K. Tsukamoto, Two-dimensional device simulation of 0.1 pm thinfilm SOI MOSFET's. IEICE Trans. Electron., vol. E75-C, no. 12, pp. 1498-1505, 1992.
14. J.-M. Hwang and G. Pollack, Novel polysilicon/TiN stacked-gate structure for fully-depleted SOI/CMOS, in IEDM Tech. Dig., pp. 345-347, 1992.
15. T. Horiuchi, T, Homma, Y. Murao, and K. Oumura, An asymmetric sidewall process for high.performance LDD MOSFET's, IEEE Trans. Electron Devices, vol. 41, no. 2, pp. 186-190, 1994.
16. Y. Omura, S. Nakashima, K. Izumi. and T. Ishii, 0.1 jm-gate, ultra thin-film CMOS devices using SIMOX substrate with 80-nm-thick buried oxide layer, in IEDM Tech. Dig., pp. 675-678, 1991.
17. J.-Y. Choi and J. G. Possum, Analysis and control of floating-body bipolar effects in fully depleted submicrometer SOI MOSFET's, IEEE Trans. Electron Devices, vol. 38, no. 6, pp. 1384-1391, 1991.
18. C. Fiegna, H. Iwai, T. Wada, M. Saito, E. Sangiorgi, and B. Ricco, Scaling the MOS transistor below 0.1 fim: methodology, device structures, and technology requirements, IEEE Trans. Electron Devices, vol. 41, no. 6, pp. 941-951, 1994.
19. F. Balestra, S. Cristoloveanu, M. Benachir, J. Brini, and T. Elewa, Dual-gate silicon-on-insulator transistor with volum inversion: a new device with greatly enhanced performance, IEEE Electron Device Lett., vol. EDL-8, no. 9, pp. 410-412, 1987.
20. S. M. Sze, Physics of Semiconductor Devices, 2d ed. New York: Wiley, 1981.
21. L. T. Su, M. J. Sherony, H. Hu, J. E. Chung, and D. A. Antoniadis, Optimization of series resistance in sub-0.2 m SOI MOSFETs, in IEDM Tech. Dig., pp. 723-726, 1993.
22. J. M. Hwang, R. Wise, E. Yee, T. Houston, and G. P. Pollack, Ultra-thin film SOI/CMOS with selective-epi source/drain for low series resistance, high drive current, in 1994 Symp. on VLSI Technol. Tech. Dig., 1994, pp. 33-34.
23. M. Chan, F. Assaderaghi, S. A. Parke, C. Hu, and P. K. Ko, Recessedchannel structure for fabricating ultra-thin SOI MOSFET with low series resistance, 1ERE Electron Device Lett., vol. 15, no. 1, pp. 22-24, 1994.