Novel polysilicon/TiN stacked-gate structure for fully-depleted SOI/CMOS

Technical Digest - International Electron Devices Meeting, IEDM

Volumn 1992-December, Issue , 1992, Pages 345-348

  Hwang, Jeong Mo ^a   Pollack, G ^a  

^a TEXAS INSTRUMENTS   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

DRAIN CURRENT; ELECTRON DEVICES; POLYCRYSTALLINE MATERIALS; POLYSILICON; THRESHOLD VOLTAGE; TITANIUM NITRIDE;

FULLY DEPLETED SOI; HOT CARRIER STRESS; LOW SUPPLY VOLTAGES; OFF-STATE LEAKAGE; POLYSILICON GATES; SATURATION DRAIN CURRENT; SUBTHRESHOLD CHARACTERISTICS; SUBTHRESHOLD SWING;

SILICON ON INSULATOR TECHNOLOGY;

EID: 85027182855     PISSN: 01631918     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IEDM.1992.307375     Document Type: Conference Paper

References (5)

1. T. Aoki, M. Tomizawa and A. Yoshii, "Design Considerations for Thin-Film SOI/CMOS Device Structures", IEEE Trans. Elec. Dev., Vol. ED-36, p. 1725, 1989.
2. L. K. Wang et al., "Enhanced Performance of Accumulation Mode 0. 5(im CMOS/SOI Operated at 300 K and 85 K", IEDM Tech. Dig., p. 679, 1991.
3. K. T. Kim et al., "Tungsten Silicide/titanium Nitride Compound Gate for Submicron CMOSFET", Symp. VLSI Technology, p. 115, 1990.
4. Technology Modeling Associate, Inc., "TMA Suprem-3: One-Dimensional Process Analysis Program", Ver sion9002, 1990.
5. D. S. Wen etal., " A Self-Aligned Inverse-T Gate Fully Overlapped LDD Device for Sub-Half Micron CMOS", IEDM Tech. Dig., p. 765, 1989.