-
2
-
-
0026105976
-
Submicron VLSI technology
-
Feb.
-
K. Seki et al., “Submicron VLSI technology,” Hitachi Rev., vol. 40, pp. 1–6, Feb. 1991.
-
(1991)
Hitachi Rev.
, vol.40
, pp. 1-6
-
-
Seki, K.1
-
3
-
-
0008001764
-
Substrate engineering for Vth scaling at low supply voltage (1.5-3 V) in VLSIs
-
Sept.
-
R. Izawa et al., “Substrate engineering for Vth- scaling at low supply voltage (1.5-3 V) in VLSIs,” in Extended Abstr. 21th Conf. Solid State Devices and Mater., Sept. 1989, pp. 121–124.
-
(1989)
Extended Abstr. 21th Conf. Solid State Devices and Mater.
, pp. 121-124
-
-
Izawa, R.1
-
4
-
-
0022700996
-
Subthreshold slope of thin-film SOI MOSFET's
-
Apr.
-
J. P. Colinge, “Subthreshold slope of thin-film SOI MOSFET's,” IEEE Electron Device Lett., vol. EDL-7, pp. 244–246, Apr. 1986.
-
(1986)
IEEE Electron Device Lett.
, vol.EDL-7
, pp. 244-246
-
-
Colinge, J.P.1
-
5
-
-
0025419522
-
A 3.8-ns CMOS 16 x 16-b multiplier using complementary pass-transistor logic
-
Apr.
-
K. Yano et al., “A 3.8-ns CMOS 16 x 16-b multiplier using complementary pass-transistor logic,” IEEE J. Solid-State Circuits, vol. 25, pp. 388–395, Apr. 1990.
-
(1990)
IEEE J. Solid-State Circuits
, vol.25
, pp. 388-395
-
-
Yano, K.1
-
6
-
-
0347346114
-
A sub-l-V swing bus architecture for future low-power ULSIs
-
June
-
Y. Nakagome et al., “A sub-l-V swing bus architecture for future low-power ULSIs,” in Symp. VLSI Circuits Dig. Tech. Papers, June 1992, pp. 82–83.
-
(1992)
Symp. VLSI Circuits Dig. Tech. Papers
, pp. 82-83
-
-
Nakagome, Y.1
-
7
-
-
85027108496
-
A 1.5V full swing BiCMOS logic circuit
-
Feb.
-
M. Hiraki et al., “A 1.5V full swing BiCMOS logic circuit, in ISSCC Dig. Tech. Papers, Feb. 1992, pp. 48-49.
-
(1992)
ISSCC Dig. Tech. Papers
, pp. 48-49
-
-
Hiraki, M.1
-
8
-
-
0025531230
-
full swing logic circuits in a complementary BiCMOS technology
-
June
-
H. J. Shin. “full swing logic circuits in a complementary BiCMOS technology,” in Symp. VLSI Circuits Dig. Tech. Papers, June 1990, pp. 89–90.
-
(1990)
Symp. VLSI Circuits Dig. Tech. Papers
, pp. 89-90
-
-
Shin, H.J.1
-
9
-
-
0039580640
-
MBiCMOS: A device and circuit technique scalable to the sub micron, sub-2V regime
-
Feb.
-
P. Raje et al., “MBiCMOS: A device and circuit technique scalable to the sub micron, sub-2V regime,” in ISSCC Dig. Tech. Papers, Feb. 1991, pp. 150–151.
-
(1991)
SSCC Dig. Tech. Papers
, pp. 150-151
-
-
Raje, P.1
-
10
-
-
0026400598
-
Quasi-complementary BiCMOS for sub-3-V digital circuits
-
June
-
K. Yano et al., “Quasi-complementary BiCMOS for sub-3-V digital circuits,” in Symp. VLSI Circuits Dig. Tech. Papers, June 1991, pp. 123–124.
-
(1991)
Symp. VLSI Circuits Dig. Tech. Papers
, pp. 123-124
-
-
Yano, K.1
-
11
-
-
0025446948
-
Performance comparison of driver configurations and fullswing BiCMOS buffers
-
June
-
H. J. Shin, “Performance comparison of driver configurations and fullswing BiCMOS buffers,” IEEE J. Solid-State Circuits, vol. 25, pp. 863–865, June 1990.
-
(1990)
IEEE J. Solid-State Circuits
, vol.25
, pp. 863-865
-
-
Shin, H.J.1
-
12
-
-
0025449455
-
Trends in megabit DRAM circuit design
-
June
-
K. Itoh, “Trends in megabit DRAM circuit design,” IEEE J. Solid-State Circuits, vol. 25, pp. 778–789, June 1990.
-
(1990)
IEEE J. Solid-State Circuits
, vol.25
, pp. 778-789
-
-
Itoh, K.1
-
13
-
-
0025537328
-
A 1.5V circuit technology for 64Mb DRAMs
-
June
-
Y. Nakagome et al., “A 1.5V circuit technology for 64Mb DRAMs,” in Symp. VLSI Circuits Dig. Tech. Papers, June 1990, pp. 17–18.
-
(1990)
Symp. VLSI Circuits Dig. Tech. Papers
, pp. 17-18
-
-
Nakagome, Y.1
-
14
-
-
0026138627
-
An experimental 1.5-V 64-Mbit DRAM
-
Apr.
-
Y. Nakagome et al., “An experimental 1.5-V 64-Mbit DRAM,” IEEE J. Solid-State Circuits, vol. 26, pp. 465–472, Apr. 1991.
-
(1991)
IEEE J. Solid-State Circuits
, vol.26
, pp. 465-472
-
-
Nakagome, Y.1
-
15
-
-
84941446360
-
Circuit techniques for 1.5-3.6V batteryoperated 64Mb DRAMs
-
Sept.
-
Y. Nakagome et al., “Circuit techniques for 1.5-3.6V batteryoperated 64Mb DRAMs,” in ESSCIRC Dig. Tech. Papers, Sept. 1990, pp. 157–160.
-
(1990)
ESSCIRC Dig. Tech. Papers
, pp. 157-160
-
-
Nakagome, Y.1
-
16
-
-
0025536507
-
A IV operating 256-kbit full CMOS SRAM
-
June
-
A. Sekiyama et al., “A IV operating 256-kbit full CMOS SRAM,” in Symp. VLSI Circuits Dig. Tech. Papers, June 1990, pp. 53–54.
-
(1990)
Symp. VLSI Circuits Dig. Tech. Papers
, pp. 53-54
-
-
Sekiyama, A.1
-
17
-
-
11744338353
-
A IV TFT-load SRAM using a two-step word-voltage method
-
Feb.
-
K. Ishibashi et al., “A IV TFT-load SRAM using a two-step word-voltage method,” in ISSCC Dig. Tech. Papers, Feb. 1992, pp. 206–207.
-
(1992)
ISSCC Dig. Tech. Papers
, pp. 206-207
-
-
Ishibashi, K.1
-
18
-
-
84941462681
-
A CMOS 40 MHz 105mW 2-step ADC
-
Feb.
-
M. Fukushima et al., “A CMOS 40 MHz 105mW 2-step ADC,” in ISSCC Dig. Tech. Papers, Feb. 1989, pp. 14–15.
-
(1989)
ISSCC Dig. Tech. Papers
, pp. 14-15
-
-
Fukushima, M.1
-
19
-
-
84941437061
-
A monolithic A/D and D/A converter with filter for broadband speech coding
-
Feb.
-
R. Lech et al., “A monolithic A/D and D/A converter with filter for broadband speech coding,” in ISSCC Dig. Tech. Papers, Feb. 1991, pp. 238–239.
-
(1991)
ISSCC Dig. Tech. Papers
, pp. 238-239
-
-
Lech, R.1
-
20
-
-
0026188098
-
An overview of smart power technology
-
July
-
B. J. Baliga, “An overview of smart power technology,” IEEE Trans. Electron Devices, vol. 38, pp. 1568–1575, July 1991.
-
(1991)
IEEE Trans. Electron Devices
, vol.38
, pp. 1568-1575
-
-
Baliga, B.J.1
-
21
-
-
84945216720
-
A 30-V, 75m mm 2 power MOSFET for intelligent driver LSIs
-
May
-
M. Morikawa et al., “A 30-V, 75m mm 2 power MOSFET for intelligent driver LSIs,” in Proc. 4th Int. Symp. Power Semicon. Dev. ICs, May 1992, pp. 150–154.
-
(1992)
Proc. 4th Int. Symp. Power Semicon. Dev. ICs
, pp. 150-154
-
-
Morikawa, M.1
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