Asymmetric sidewall process for high performance LDD MOSFET's

IEEE Transactions on Electron Devices

Volumn 41, Issue 2, 1994, Pages 186-190

  Horiuchi, Tadahiko ^a   Homma, Tetsuya ^a   Murao, Yukinobu ^a   Okumura, Koichiro ^a  

^a NEC CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; DEPOSITION; HOT CARRIERS; MASKS; PERFORMANCE; RELIABILITY; SEMICONDUCTOR DEVICE MANUFACTURE; SEMICONDUCTOR DEVICE STRUCTURES;

ASYMMETRIC SIDEWALL PROCESS; SELECTIVE OXIDE DEPOSITION PROCESS;

MOSFET DEVICES;

EID: 0028380786     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/16.277381     Document Type: Article

References (9)

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2. A. Bryant B. El-Kareh T. Furukawa W. Noble E. Nowak W. Tonti A fundamental performance limit of optimized 3.3 V subquater micron fully overlapped LDD MOSFETs Symp. VLSI Tech. Dig. 45 46 Symp. VLSI Tech. Dig. 1990
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4. L. T. Su J. A. Yasaitis D. A. Antoniadis A high-performance scalable submicron MOSFET for mixed analog/digital applications IEDM Tech. Dig. 367 370 1991
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