-
1
-
-
0000950606
-
The Roles of FPGAs in Reprogrammable Systems
-
S. Hauck, "The Roles of FPGAs in Reprogrammable Systems," Proceedings of the IEEE, vol. 86, pp. 615-638, 1998.
-
(1998)
Proceedings of the IEEE
, vol.86
, pp. 615-638
-
-
Hauck, S.1
-
3
-
-
24344435801
-
-
University College London, Image Processing Group, London, U. K., Technical Report July 2000-July 2001
-
M. R. B. Forshaw, K. Nikolic, A. Sadek, "3rd Annual Report, Autonomous Nanoelectronic Systems With Extended Replication and Signalling, ANSWERS," University College London, Image Processing Group, London, U. K., Technical Report July 2000-July 2001, 2001.
-
(2001)
3rd Annual Report, Autonomous Nanoelectronic Systems With Extended Replication and Signalling, ANSWERS
-
-
Forshaw, M.R.B.1
Nikolic, K.2
Sadek, A.3
-
4
-
-
0032164444
-
Defect Tolerance in VLSI Circuits: Techniques and Yield Analysis
-
I. Koren, Z. Koren, "Defect Tolerance in VLSI Circuits: Techniques and Yield Analysis," Proceedings of the IEEE, vol. 86, pp. 1819-1836, 1998.
-
(1998)
Proceedings of the IEEE
, vol.86
, pp. 1819-1836
-
-
Koren, I.1
Koren, Z.2
-
5
-
-
0031682050
-
How Much Logic Should Go in an FPGA Logic Block?
-
V. Betz, Jonathan Rose, "How Much Logic Should Go in an FPGA Logic Block?," IEEE Design and Test of Computers, vol. 15, pp. 10-15, 1998.
-
(1998)
IEEE Design and Test of Computers
, vol.15
, pp. 10-15
-
-
Betz, V.1
Rose, J.2
-
6
-
-
0031639556
-
More Wires and Fewer LUTs: A Design Methodology for FPGAs
-
A. Takahara, Miyazaki, T., Murooka, T., Katayama, M., Hayashi, K., Tsutsui, A., Ichimori, T., Fukami, K-n., "More Wires and Fewer LUTs: A Design Methodology for FPGAs," presented at ACM/SIGDA Sixth International Symposium on Field programmable Gate Arrays, 1998.
-
(1998)
ACM/SIGDA Sixth International Symposium on Field Programmable Gate Arrays
-
-
Takahara, A.1
Miyazaki, T.2
Murooka, T.3
Katayama, M.4
Hayashi, K.5
Tsutsui, A.6
Ichimori, T.7
Fukami, K.-N.8
-
8
-
-
0003975428
-
-
2nd ed: European Commission IST Programme - Future and Emerging Technologies
-
R. Compano (ed.), "Technology Roadmap for Nanoelectronics," 2nd ed: European Commission IST Programme - Future and Emerging Technologies, 2000.
-
(2000)
Technology Roadmap for Nanoelectronics
-
-
Compano, R.1
-
9
-
-
0012561327
-
Coming Challenges in Microarchitecture and Architecture
-
R. Ronen, A. Mendelson, K. Lai, Shih-Lien Lu, F. Pollack, J. P. Shen, "Coming Challenges in Microarchitecture and Architecture," Proceedings of the IEEE, vol. 98, pp. 325-340, 2001.
-
(2001)
Proceedings of the IEEE
, vol.98
, pp. 325-340
-
-
Ronen, R.1
Mendelson, A.2
Lai, K.3
Lu, S.-L.4
Pollack, F.5
Shen, J.P.6
-
11
-
-
0034617249
-
Carbon Nanotube-Based Nonvolatile Random Access Memory for Molecular Computing
-
T. Rueckes, K. Kim, E. Joselevich, G. Y. Tseng, C-L. Cheung, C. M. Lieber, "Carbon Nanotube-Based Nonvolatile Random Access Memory for Molecular Computing," Science, vol. 289, pp. 94-97, 2000.
-
(2000)
Science
, vol.289
, pp. 94-97
-
-
Rueckes, T.1
Kim, K.2
Joselevich, E.3
Tseng, G.Y.4
Cheung, C.-L.5
Lieber, C.M.6
-
12
-
-
0035834444
-
Logic Circuits with Carbon Nanotube Transistors
-
A. Bachtold, P. Hadley, T. Nakanishi, C. Dekker, "Logic Circuits with Carbon Nanotube Transistors," Science, vol. 294, pp. 1317-1320, 2001.
-
(2001)
Science
, vol.294
, pp. 1317-1320
-
-
Bachtold, A.1
Hadley, P.2
Nakanishi, T.3
Dekker, C.4
-
13
-
-
0346207532
-
Array-Based Architecture for Molecular Electronics
-
Cambridge, Massachusetts
-
A. DeHon, "Array-Based Architecture for Molecular Electronics," presented at First Workshop on Non-Silicon Computation (NSC-1), Cambridge, Massachusetts, 2002.
-
(2002)
First Workshop on Non-Silicon Computation (NSC-1)
-
-
DeHon, A.1
-
14
-
-
0027266749
-
Quantum Cellular Automata
-
C. S. Lent, Tougaw, P. D., Porod, W., Bernstein, G. H., "Quantum Cellular Automata," Nanotechnology, vol. 4, pp. 49-57, 1993.
-
(1993)
Nanotechnology
, vol.4
, pp. 49-57
-
-
Lent, C.S.1
Tougaw, P.D.2
Porod, W.3
Bernstein, G.H.4
-
15
-
-
3142722452
-
A Potentially Implementable FPGA for Quantum Dot Cellular Automata
-
Cambridge, Massachusetts
-
M. T. Niemier, Arun F. Rodrigues, Peter M. Kogge, "A Potentially Implementable FPGA for Quantum Dot Cellular Automata," presented at First Workshop on Non-Silicon Computation (NSC-1), Cambridge, Massachusetts, 2002.
-
(2002)
First Workshop on Non-Silicon Computation (NSC-1)
-
-
Niemier, M.T.1
Rodrigues, A.F.2
Kogge, P.M.3
-
16
-
-
0036568258
-
Field Programmable Spin-Logic Realized with Tunnelling-Magnetoresistance Devices
-
R. Richter, H. Boeve, L. Bär, J. Bangert, G. Rupp, G. Reiss, J. Wecker, "Field Programmable Spin-Logic Realized with Tunnelling-Magnetoresistance Devices," Solid-State Electronics, vol. 46, pp. 639-643, 2002.
-
(2002)
Solid-State Electronics
, vol.46
, pp. 639-643
-
-
Richter, R.1
Boeve, H.2
Bär, L.3
Bangert, J.4
Rupp, G.5
Reiss, G.6
Wecker, J.7
-
17
-
-
0035423513
-
Pi-Gate SOI MOSFET
-
J.-T. Park, J.-P. Colinge, C.H. Diaz, "Pi-Gate SOI MOSFET," IEEE Electron Device Letters, vol. 22, pp. 405-406, 2001.
-
(2001)
IEEE Electron Device Letters
, vol.22
, pp. 405-406
-
-
Park, J.-T.1
Colinge, J.-P.2
Diaz, C.H.3
-
19
-
-
0032640532
-
An Innovative, Segmented High Performance FPGA Family with Variable-Grain-Architecture and Wide-Gating Functions
-
O. Agrawal, H. Chang, B. Sharpe-Geisler, N. Schmitz, B. Nguyen, J. Wong, G. Tran, F. Fontana, W. Harding, "An Innovative, Segmented High Performance FPGA Family with Variable-Grain-Architecture and Wide-Gating Functions," presented at ACM/SIGDA Seventh International Symposium on Field Programmable Gate Arrays, 1999.
-
(1999)
ACM/SIGDA Seventh International Symposium on Field Programmable Gate Arrays
-
-
Agrawal, O.1
Chang, H.2
Sharpe-Geisler, B.3
Schmitz, N.4
Nguyen, B.5
Wong, J.6
Tran, G.7
Fontana, F.8
Harding, W.9
-
20
-
-
0003849991
-
Reconfigurable Architectures for General-Purpose Computing
-
MIT, Massachusetts, October
-
A. DeHon, "Reconfigurable Architectures for General-Purpose Computing," MIT, Massachusetts, A.I. Technical Report 1586, October, 1996.
-
(1996)
A.I. Technical Report
-
-
DeHon, A.1
-
21
-
-
33646924323
-
Impact of Small Process Geometries on Microarchitectures in Systems on a Chip
-
D. Sylvester, Keutzer, K., "Impact of Small Process Geometries on Microarchitectures in Systems on a Chip," Proceedings of the IEEE, vol. 89, pp. 467-489, 2001.
-
(2001)
Proceedings of the IEEE
, vol.89
, pp. 467-489
-
-
Sylvester, D.1
Keutzer, K.2
-
22
-
-
0035019250
-
Interconnect Pipelining in a Throughput-Intensive FPGA Architecture
-
Monterey, CA
-
A. Singh, A. Mukherjee, M. Marek-Sadowska, "Interconnect Pipelining in a Throughput-Intensive FPGA Architecture," presented at Ninth International Symposium on Field programmable Gate Arrays, Monterey, CA, 2001.
-
(2001)
Ninth International Symposium on Field Programmable Gate Arrays
-
-
Singh, A.1
Mukherjee, A.2
Marek-Sadowska, M.3
-
24
-
-
0032592096
-
Design Challenges of Technology Scaling
-
S. Borkar, "Design Challenges of Technology Scaling," IEEE Micro, vol. 19, pp. 23-29, 1999.
-
(1999)
IEEE Micro
, vol.19
, pp. 23-29
-
-
Borkar, S.1
-
25
-
-
33646922057
-
The Future of Wires
-
R. Ho, K.W. Mai, M.A. Horowitz, "The Future of Wires," Proceedings of the IEEE, vol. 89, pp. 490-504, 2001.
-
(2001)
Proceedings of the IEEE
, vol.89
, pp. 490-504
-
-
Ho, R.1
Mai, K.W.2
Horowitz, M.A.3
-
26
-
-
0033221575
-
Rethinking Deep-Submicron Circuit Design
-
D. Sylvester, Keutzer, K., "Rethinking Deep-Submicron Circuit Design," Computer, vol. 32, pp. 25-33, 1999.
-
(1999)
Computer
, vol.32
, pp. 25-33
-
-
Sylvester, D.1
Keutzer, K.2
-
27
-
-
0026837106
-
The Effect of Logic Block Architecture on FPGA Performance
-
S. Singh, J. Rose, P. Chow, D. Lewis, "The Effect of Logic Block Architecture on FPGA Performance," IEEE Journal of Solid-State Circuits, vol. 27, pp. 281-287, 1992.
-
(1992)
IEEE Journal of Solid-State Circuits
, vol.27
, pp. 281-287
-
-
Singh, S.1
Rose, J.2
Chow, P.3
Lewis, D.4
-
28
-
-
0033723235
-
The Effect of LUT and Cluster Size on Deep-Submicron FPGA Performance and Density
-
Monterey, CA, USA
-
E. Ahmed, J. Rose, "The Effect of LUT and Cluster Size on Deep-Submicron FPGA Performance and Density," presented at FPGA 2000, Monterey, CA, USA, 2000.
-
(2000)
FPGA 2000
-
-
Ahmed, E.1
Rose, J.2
-
33
-
-
0035714368
-
Triple-Self-Aligned, Planar Double-Gate MOSFETs: Devices and Circuits
-
Washington, DC
-
K. W. Guarini, Solomon, P.M., Zhang, Y., Chan, K.K., Jones, E.C., Cohen, G.M., Krasnoperova, A., Ronay, M., Dokumaci, O., Bucchignano, J.J., Cabral, C., Jr., Lavoie, C., Ku, V., Boyd, D.C., Petrarca, K.S., Babich, I.V., Treichler, J., Kozlowski, P.M., "Triple-Self-Aligned, Planar Double-Gate MOSFETs: Devices and Circuits," presented at International New Electron Devices Meeting, Washington, DC, 2001.
-
(2001)
International New Electron Devices Meeting
-
-
Guarini, K.W.1
Solomon, P.M.2
Zhang, Y.3
Chan, K.K.4
Jones, E.C.5
Cohen, G.M.6
Krasnoperova, A.7
Ronay, M.8
Dokumaci, O.9
Bucchignano, J.J.10
Cabral, C.11
Lavoie, C.12
Ku, V.13
Boyd, D.C.14
Petrarca, K.S.15
Babich, I.V.16
Treichler, J.17
Kozlowski, P.M.18
-
35
-
-
84962906715
-
-
falcon.ecn.purdue.edu:8080/mosfet/10nmstructure.pdf
-
Z. Ren, R. Venugopal, S. Datta, M. Lundstrom, D. Jovanovic, J. Fossum, "Idealized SOI-Si Double Gate NMOSFET Device, Rev. 12-8-00", falcon.ecn.purdue.edu:8080/mosfet/10nmstructure.pdf
-
Idealized SOI-Si Double Gate NMOSFET Device, Rev. 12-8-00
-
-
Ren, Z.1
Venugopal, R.2
Datta, S.3
Lundstrom, M.4
Jovanovic, D.5
Fossum, J.6
-
36
-
-
0035714565
-
Experimental Evaluation of Carrier Transport and Device Design for Planar Symmetric/Asymmetric Double-Gate/Ground-Plane CMOSFETs
-
IEDM Technical Digest. International, Washington, DC, 2001
-
M. Ieong, Jones, E.C., Kanarsky, T., Ren, Z., Dokumaci, O., Roy, R.A., Shi, L., Furukawa, T., Taur, Y., Miller, R.J., Wong, H.-S.P., "Experimental Evaluation of Carrier Transport and Device Design for Planar Symmetric/Asymmetric Double-Gate/Ground-Plane CMOSFETs," presented at Electron Devices Meeting, 2001. IEDM Technical Digest. International, Washington, DC, 2001.
-
(2001)
Electron Devices Meeting
-
-
Ieong, M.1
Jones, E.C.2
Kanarsky, T.3
Ren, Z.4
Dokumaci, O.5
Roy, R.A.6
Shi, L.7
Furukawa, T.8
Taur, Y.9
Miller, R.J.10
Wong, H.-S.P.11
-
37
-
-
0034453428
-
Gate Length Scaling and Threshold Voltage Control of Double-Gate MOSFETs
-
San Francisco, CA, USA
-
L. Chang, Tang, S., Tsu-Jae King, Bokor, J., Chenming Hu, "Gate Length Scaling and Threshold Voltage Control of Double-Gate MOSFETs," presented at International Electron Devices Meeting, San Francisco, CA, USA, 2000.
-
(2000)
International Electron Devices Meeting
-
-
Chang, L.1
Tang, S.2
King, T.-J.3
Bokor, J.4
Hu, C.5
-
38
-
-
0031683740
-
Novel Dual-Gate HEMT Utilising Multiple Split Gates
-
N. J. Collier, Cleaver, J. R. A., "Novel Dual-Gate HEMT Utilising Multiple Split Gates," Microelectronic Engineering, vol. 41-42, pp. 457-460, 1998.
-
(1998)
Microelectronic Engineering
, vol.41-42
, pp. 457-460
-
-
Collier, N.J.1
Cleaver, J.R.A.2
-
39
-
-
0029378517
-
A 48.1 ps HEMT DCFL NAND Circuit with a Dual Gate Structure
-
H. Suehiro, Miyata, T., Hara, N., Kuroda, S., "A 48.1 ps HEMT DCFL NAND Circuit with a Dual Gate Structure," Solid-State Electronics, vol. 38, pp. 1717-1721, 1995.
-
(1995)
Solid-State Electronics
, vol.38
, pp. 1717-1721
-
-
Suehiro, H.1
Miyata, T.2
Hara, N.3
Kuroda, S.4
-
40
-
-
0036642887
-
Planar and Vertical Double Gate Concepts
-
T. Schulz, W. Rösner, E. Landgraf, L. Risch, U. Langmann, "Planar and Vertical Double Gate Concepts," Solid-State Electronics, vol. 46, pp. 985-989, 2002.
-
(2002)
Solid-State Electronics
, vol.46
, pp. 985-989
-
-
Schulz, T.1
Rösner, W.2
Landgraf, E.3
Risch, L.4
Langmann, U.5
-
41
-
-
84907562717
-
Double-Gate MOSFETs: Is Gate Alignment Mandatory?
-
Nuremberg, Germany
-
F. Allibert, A. Zaslavsky, J. Pretet, S. Cristoloveanu, "Double-Gate MOSFETs: Is Gate Alignment Mandatory?," presented at European Solid-State Device Research Conference, Nuremberg, Germany, 2001.
-
(2001)
European Solid-State Device Research Conference
-
-
Allibert, F.1
Zaslavsky, A.2
Pretet, J.3
Cristoloveanu, S.4
-
42
-
-
0030122781
-
Theoretical Consideration of a New Nanometer Transistor Using Metal/Insulator Tunnel-Junction
-
K. Fujimaru, Hideki Matsumura, "Theoretical Consideration of a New Nanometer Transistor Using Metal/Insulator Tunnel-Junction," Japanese Journal of Applied Physics, vol. 35, Part 1, pp. 1781-1786, 1996.
-
(1996)
Japanese Journal of Applied Physics
, vol.35
, pp. 1781-1786
-
-
Fujimaru, K.1
Matsumura, H.2
-
43
-
-
0141769693
-
Carbon Nanotube Inter- and Intramolecular Logic Gates
-
V. Derycke, Martel, R., Appenzeller, J., Avouris, Ph., "Carbon Nanotube Inter- and Intramolecular Logic Gates," Nano Letters, vol. 1, pp. 453-456, 2001.
-
(2001)
Nano Letters
, vol.1
, pp. 453-456
-
-
Derycke, V.1
Martel, R.2
Appenzeller, J.3
Avouris, Ph.4
-
44
-
-
79956022434
-
Vertical Scaling of Carbon Nanotube Field-Effect Transistors using Top Gate Electrodes
-
S. J. Wind, Appenzeller, J., Martel, R., Derycke, V., Avouris, Ph., "Vertical Scaling of Carbon Nanotube Field-Effect Transistors using Top Gate Electrodes," Applied Physics Letters, vol. 80, pp. 3817-3819, 2002.
-
(2002)
Applied Physics Letters
, vol.80
, pp. 3817-3819
-
-
Wind, S.J.1
Appenzeller, J.2
Martel, R.3
Derycke, V.4
Avouris, Ph.5
-
45
-
-
0026820499
-
Multivalued SRAM Cell Using Resonant Tunneling Diodes
-
S.-J. Wei, Lin, H.C., "Multivalued SRAM Cell Using Resonant Tunneling Diodes," IEEE Journal of Solid-State Circuits, vol. 27, pp. 212-216, 1992.
-
(1992)
IEEE Journal of Solid-State Circuits
, vol.27
, pp. 212-216
-
-
Wei, S.-J.1
Lin, H.C.2
-
46
-
-
0032635955
-
Tunnelling-Based SRAM
-
J. P. A. van der Wagt, "Tunnelling-Based SRAM," Nanotechnology, vol. 10, pp. 174-186, 1999.
-
(1999)
Nanotechnology
, vol.10
, pp. 174-186
-
-
Van Der Wagt, J.P.A.1
-
47
-
-
0033115890
-
A New RTD-FET Logic Family
-
R. H. Mathews, Sage, J.P., Sollner, T.C.L.G., Calawa, S.D., Chang-Lee Chen, Mahoney, L.J., Maki, P.A., Molvar, K.M., "A New RTD-FET Logic Family," Proceedings of the IEEE, vol. 87, pp. 596-605, 1999.
-
(1999)
Proceedings of the IEEE
, vol.87
, pp. 596-605
-
-
Mathews, R.H.1
Sage, J.P.2
Sollner, T.C.L.G.3
Calawa, S.D.4
Chen, C.-L.5
Mahoney, L.J.6
Maki, P.A.7
Molvar, K.M.8
-
48
-
-
0026915728
-
Nine-state Resonant Tunneling Diode Memory
-
A. C. Seabaugh, Y.-C. Kao, H.-T. Yuan, "Nine-state Resonant Tunneling Diode Memory," IEEE Electron Device Letters, vol. 13, pp. 479-481, 1992.
-
(1992)
IEEE Electron Device Letters
, vol.13
, pp. 479-481
-
-
Seabaugh, A.C.1
Kao, Y.-C.2
Yuan, H.-T.3
-
49
-
-
0035083659
-
"P-on-N" Si Interband Tunnel Diode Grown by Molecular Beam Epitaxy
-
K. D. Hobart, P. E. Thompson, S. L. Rommel, T. E. Dillon, P. R. Berger, D. S. Simons, P. H. Chi, ""P-on-N" Si Interband Tunnel Diode Grown by Molecular Beam Epitaxy," Journal of Vacuum Science and Technology B, vol. 19, pp. 290-293, 2001.
-
(2001)
Journal of Vacuum Science and Technology B
, vol.19
, pp. 290-293
-
-
Hobart, K.D.1
Thompson, P.E.2
Rommel, S.L.3
Dillon, T.E.4
Berger, P.R.5
Simons, D.S.6
Chi, P.H.7
-
50
-
-
0035829523
-
A PNP Si Resonant Interband Tunnel Diode with Symmetrical NDR
-
N. Jin, Paul R. Berger, Sean L. Rommel, Phillip E. Thompson, Karl D. Hobart, "A PNP Si Resonant Interband Tunnel Diode with Symmetrical NDR," Electronics Letters, vol. 37, pp. 1412-1414, 2001.
-
(2001)
Electronics Letters
, vol.37
, pp. 1412-1414
-
-
Jin, N.1
Berger, P.R.2
Rommel, S.L.3
Thompson, P.E.4
Hobart, K.D.5
-
51
-
-
0029714354
-
Plasma: An FPGA for Million Gate Systems
-
Monterey, CA USA
-
R. Amerson, R. Carter, W. Culbertson, P. Kuekes, G. Snider, L. Albertson, "Plasma: an FPGA for Million Gate Systems," presented at ACM Fourth International Symposium on Field-Programmable Gate Arrays, Monterey, CA USA, 1996.
-
(1996)
ACM Fourth International Symposium on Field-Programmable Gate Arrays
-
-
Amerson, R.1
Carter, R.2
Culbertson, W.3
Kuekes, P.4
Snider, G.5
Albertson, L.6
-
52
-
-
18544364440
-
-
Master's Thesis, Department of ECE, Northwestern University, Evanston, IL, USA
-
C. Compton, "Programming Architectures for Run-Time Reconfigurable Systems," Master's Thesis, Department of ECE, Northwestern University, Evanston, IL, USA, 2000.
-
(2000)
Programming Architectures for Run-Time Reconfigurable Systems
-
-
Compton, C.1
-
53
-
-
0032027733
-
Clock-cycle Estimation and Test Challenges for Future Microprocessors
-
P. D. Fisher, R. Nesbitt, "Clock-cycle Estimation and Test Challenges for Future Microprocessors," IEEE Circuits and Devices, pp. 37, 1998.
-
(1998)
IEEE Circuits and Devices
, pp. 37
-
-
Fisher, P.D.1
Nesbitt, R.2
-
55
-
-
0030079495
-
Capacitance of Nanostructures
-
T. Ohba, K. Natori, "Capacitance of Nanostructures," Japanese Journal of Applied Physics, vol. 35 Part 1, pp. 1366-1369, 1996.
-
(1996)
Japanese Journal of Applied Physics
, vol.35
, pp. 1366-1369
-
-
Ohba, T.1
Natori, K.2
|