|
Volumn , Issue , 1998, Pages 12-19
|
More wires and fewer LUTs: A design methodology for FPGAs
a a a a a a a a
a
NTT CORPORATION
(Japan)
|
Author keywords
[No Author keywords available]
|
Indexed keywords
COMPUTER ARCHITECTURE;
DECISION THEORY;
LOGIC DESIGN;
TABLE LOOKUP;
WIRING RESOURCES;
FIELD PROGRAMMABLE GATE ARRAYS;
|
EID: 0031639556
PISSN: None
EISSN: None
Source Type: Conference Proceeding
DOI: None Document Type: Conference Paper |
Times cited : (12)
|
References (13)
|