Interconnect pipelining in a throughput-intensive FPGA architecture

ACM/SIGDA International Symposium on Field Programmable Gate Arrays - FPGA

Volumn , Issue , 2001, Pages 153-160

  Singh, A ^a   Mukherjee, A ^a   Marek Sadowska, M ^a  

^a University of California   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER ARCHITECTURE; EMBEDDED SYSTEMS; PIPELINE PROCESSING SYSTEMS; TREES (MATHEMATICS);

PASS TRANSISTOR LOGIC (PTL);

FIELD PROGRAMMABLE GATE ARRAYS;

EID: 0035019250     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/360276.360323     Document Type: Conference Paper

References (27)