The test of time: Clock-cycle estimation and test challenges for future microprocessors

IEEE Circuits and Devices Magazine

Volumn 14, Issue 2, 1998, Pages 37-44

  Fisher, Phil D ^a   Nesbitt, Robert ^a  

^a SEMATECH   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

APPLICATION SPECIFIC INTEGRATED CIRCUITS; COMPUTER AIDED DESIGN; COMPUTER AIDED SOFTWARE ENGINEERING; COMPUTER SIMULATION; INTERCONNECTION NETWORKS; LOGIC GATES; MATHEMATICAL MODELS; NAND CIRCUITS; RANDOM ACCESS STORAGE; TIMING CIRCUITS;

DYNAMIC RANDOM ACCESS MEMORY (DRAM);

MICROPROCESSOR CHIPS;

EID: 0032027733     PISSN: 87553996     EISSN: None     Source Type: Journal    
DOI: 10.1109/101.666590     Document Type: Article

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