Defect tolerance in VLSI circuits: Techniques and yield analysis

Proceedings of the IEEE

Volumn 86, Issue 9, 1998, Pages 1819-1836

  Koren, Israel ^a   Koren, Zahava ^a  

^a University of Massachusetts at Amherst   (United States)

Author keywords

Critical area; Defect tolerance; Defects; Faults; Floor plan; Layout; Redundancy; Yield; Yield model

Indexed keywords

ELECTRIC NETWORK SYNTHESIS; FAILURE ANALYSIS; INTEGRATED CIRCUIT MANUFACTURE;

YIELD ENHANCEMENT TECHNIQUES;

VLSI CIRCUITS;

EID: 0032164444     PISSN: 00189219     EISSN: None     Source Type: Journal    
DOI: 10.1109/5.705525     Document Type: Article

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