Enabling interposer-based disintegration of multi-core processors

Proceedings of the Annual International Symposium on Microarchitecture, MICRO

Volumn 05-09-December-2015, Issue , 2015, Pages 546-558

  Kannan, Ajaykumar ^a   Jerger, Natalie Enright ^a,b   Loh, Gabriel H ^b  

^a UNIVERSITY OF TORONTO   (Canada)

^b ADVANCED MICRO DEVICES   (United States)

Author keywords

die stacking; network on chip; silicon interposer

Indexed keywords

COMPUTER ARCHITECTURE; COSTS; ECONOMIC AND SOCIAL EFFECTS; SERVERS; VLSI CIRCUITS;

DIE STACKING; MULTI-CORE CPUS; MULTI-CORE PROCESSOR; MULTI-CORE SYSTEMS; PERFORMANCE CHALLENGES; PERFORMANCE COSTS; ROUTING RESOURCES; SILICON INTERPOSERS;

NETWORK-ON-CHIP;

EID: 84959895721     PISSN: 10724451     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/2830772.2830808     Document Type: Conference Paper

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