Reliability aware throughput management of chip multi-processor architecture via thread migration

Journal of Supercomputing

Volumn 72, Issue 4, 2016, Pages 1363-1380

  Pouyan, Fatemeh ^a   Azarpeyvand, Ali ^b   Safari, Saeed ^a   Fakhraie, Sied Mehdi ^a  

^a UNIVERSITY OF TEHRAN   (Iran)

^b UNIVERSITY OF ZANJAN   (Iran)

Author keywords

Architectural vulnerability factor; Chip multiprocessor; Performance; Reliability; Simultaneous multithreading; Soft error

Indexed keywords

ERROR CORRECTION; MAPPING; MEMORY ARCHITECTURE; MULTIPROCESSING SYSTEMS; MULTITASKING; PROGRAM PROCESSORS; RADIATION HARDENING; RELIABILITY; SCHEDULING; THROUGHPUT;

ARCHITECTURAL VULNERABILITY FACTOR; CHIP MULTIPROCESSOR; PERFORMANCE; SIMULTANEOUS MULTI-THREADING; SOFT ERROR;

REDUNDANCY;

EID: 84958775828     PISSN: 09208542     EISSN: 15730484     Source Type: Journal    
DOI: 10.1007/s11227-016-1665-3     Document Type: Article

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