Measuring Architectural Vulnerability Factors

IEEE Micro

Volumn 23, Issue 6, 2003, Pages 70-75

  Mukherjee, Shubhendu S ^a,c   Weaver, Christopher T ^a,d   Emer, Joel ^a   Reinhardt, Steven K ^a,b   Austin, Todd ^b  

^a INTEL CORPORATION   (United States)

^b UNIVERSITY OF MICHIGAN   (United States)

^c University of Michigan ^*  (United States)

^d Intel's Massachusetts MDC   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ARCHITECTURAL VULNERABILITY FACTORS (AVM); MICROARCHITECTURE; PARTICLE FLUX;

BENCHMARKING; DIFFUSION; ERROR ANALYSIS; ESTIMATION; MATHEMATICAL MODELS; STATIC RANDOM ACCESS STORAGE; TRANSISTORS;

MICROPROCESSOR CHIPS;

EID: 1342303703     PISSN: 02721732     EISSN: None     Source Type: Journal    
DOI: 10.1109/MM.2003.1261389     Document Type: Review

References (14)

1. J.F. Ziegler et al., "IBM Experiments in Soft Fails in Computer Electronics (1978-1994)," IBM J. Research and Development, vol. 40, no. 1, Jan. 1996, pp. 3-18.
2. R. Baumann, "Soft Errors in Commercial Semiconductor Technology: Overview and Scaling Trends," IEEE 2002 Reliability Physics Symp. Tutorial Notes, Reliability Fundamentals, IEEE Press, 2002, pp. 121-01.1-121-01.14.
3. E. Normand, "Single-Event Upset at Ground Level," IEEE Trans. Nuclear Science, vol. 43, no. 6, Dec. 1996, pp. 2742-2750.
4. H. Ando et al., "A 1.3GHz Fifth Generation SPARC64 Microprocessor," Proc. IEEE Int'l Solid-State Circuits Conf. (ISSCC 03), IEEE Press, 2003, pp. 246-247.
5. T. Calin, M. Nicolaidis, and R. Velazco, "Upset Hardened Memory Design for Submicron CMOS Technology," IEEE Trans. Nuclear Science, vol. 43, no. 6, Dec. 1996, pp. 2874-2878.
6. T.J. Slegel et al., "IBM's S/390 G5 Micro-processor Design," IEEE Micro, vol. 19, no. 2, Mar.-Apr. 1999, pp. 12-23.
7. T.M. Austin, "DIVA: A Reliable Substrate for Deep Submicron Microarchitecture Design," Proc. 32nd Ann. Int'l Symp. Microarchitecture (MICRO-32), IEEE CS Press, 1999, pp. 196-207.
8. S.S. Mukherjee, M. Kontz, and S.K. Reinhardt, "Detailed Design and Evaluation of Redundant Multithreading Alternatives," Proc. 29th Ann, Int'l Symp. Computer Architecture (ISCA 02), IEEE CS Press, 2002, pp. 99-110.
9. S.K. Reinhardt and S.S. Mukherjee, "Transient Fault Detection via Simultaneous Multithreading," Proc. 27th Ann. Int'l Symp. Computer Architecture (ISCA 2000), ACM Press, 2000, pp. 25-36.
10. E.D. Lazowska et al., Quantitative System Performance, pp. 42-46, Prentice-Hall, 1984.
11. J. Emer et al., "Asim: A Performance Model Framework," Computer, vol. 35, no. 2, Feb. 2002, pp. 68-76.
12. S.S. Mukherjee et al., "A Systematic Methodology to Compute the Architectural Vulnerability Factors of a High-Performance Microprocessor," to be published in Proc. 36th Ann. Int'l Symp. Microarchitecture (MICRO-36), IEEE CS Press, 2003.
13. N. Wang, M. Fertig, and S. Patel, "Y-Branches: When You Come to a Fork in the Road, Take It," Proc. 12th Int'l Conf. Parallel Architectures and Compilation Techniques (PACT 03), IEEE CS Press, 2003, pp. 56-67.
14. S. Kim and A.K. Somani, "Soft Error Sensitivity Characterization for Microprocessor Dependability Enhancement Strategy," Proc. Int'l Conf. Dependable Systems and Networks (DSN 02), IEEE CS Press, 2002, pp. 416-428.