Transient Fault Tolerance on Chip Multiprocessor based on Dual and Triple Core Redundancy1

Proceedings of the 14th IEEE Pacific Rim International Symposium on Dependable Computing, PRDC 2008

Volumn , Issue , 2008, Pages 273-280

  Gong, Rui ^a   Dai, Kui ^a   Wang, Zhiying ^a  

^a NATIONAL UNIVERSITY OF DEFENSE TECHNOLOGY   (China)

Author keywords

[No Author keywords available]

Indexed keywords

BANDWIDTH; ELECTRIC REACTORS; ERRORS; FAILURE ANALYSIS; FAULT DETECTION; FAULT TOLERANCE; FAULT TOLERANT COMPUTER SYSTEMS; FAULT TREE ANALYSIS; MICROPROCESSOR CHIPS; MULTIPROCESSING SYSTEMS; QUALITY ASSURANCE; REDUNDANCY; SYSTEMS ANALYSIS; TELECOMMUNICATION SYSTEMS; THERMAL CONDUCTIVITY OF SOLIDS;

BANDWIDTH DEMANDS; CHIP-MULTIPROCESSORS; COMMUNICATION BANDWIDTHS; CORE LEVELS; FAULT RECOVERIES; NEW APPROACHES; SINGLE-EVENT UPSETS; TRANSIENT FAULTS; TRIPLE MODULAR REDUNDANCIES;

RELIABILITY;

EID: 60349111201     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/PRDC.2008.40     Document Type: Conference Paper

References (9)

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