Opportunistic transient-fault detection

IEEE Micro

Volumn 26, Issue 1, 2006, Pages 92-99

  Gomaa, Mohamed A ^a   Vijaykumar, T N ^a  

^a PURDUE UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; ELECTRIC POTENTIAL; MICROPROCESSOR CHIPS; MULTIPROCESSING SYSTEMS; RELIABILITY; SERVERS; TRANSISTORS;

REDUNDANCY-BASED FAULT DETECTION; REUSE-BASED FAULT DETECTION; TRANSIENT-FAULT DETECTION;

FAULT TOLERANT COMPUTER SYSTEMS;

EID: 33644899918     PISSN: 02721732     EISSN: None     Source Type: Journal    
DOI: 10.1109/MM.2006.20     Document Type: Article

References (8)

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8. S. S. Mukherjee et al., "A Systematic Methodology to Compute the Architectural Vulnerability Factors for a High-Performance Microprocessor," Proc. 36th Ann. Int'l Symp. Microarchitecture (Micro-36), IEEE CS Press, 2003, pp. 29-40.